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CY7C139AV-25JC PDF预览

CY7C139AV-25JC

更新时间: 2024-11-26 22:25:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
20页 303K
描述
3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM

CY7C139AV-25JC 数据手册

 浏览型号CY7C139AV-25JC的Datasheet PDF文件第2页浏览型号CY7C139AV-25JC的Datasheet PDF文件第3页浏览型号CY7C139AV-25JC的Datasheet PDF文件第4页浏览型号CY7C139AV-25JC的Datasheet PDF文件第5页浏览型号CY7C139AV-25JC的Datasheet PDF文件第6页浏览型号CY7C139AV-25JC的Datasheet PDF文件第7页 
25/0251  
CY7C138AV/144AV/006AV  
CY7C139AV/145AV/016AV  
CY7C007AV/017AV  
3.3V 4K/8K/16K/32K x 8/9  
Dual-Port Static RAM  
• Fully asynchronous operation  
• Automatic power-down  
Features  
• True Dual-Ported memory cells which allow simulta-  
neous access of the same memory location  
• 4K/8K/16K/32K x 8 organizations  
(CY7C0138AV/144AV/006AV/007AV)  
• 4K/8K/16K/32K x 9 organizations  
(CY7C0139AV/145AV/016AV/017AV)  
• 0.35-micron CMOS for optimum speed/power  
• High-speed access: 20/25 ns  
• Low operating power  
• Expandabledatabusto16/18bitsormoreusingMaster/  
Slave chip select when using more than one device  
• On-chip arbitration logic  
• Semaphores included to permit software handshaking  
between ports  
• INT flag for port-to-port communication  
• Pin select for Master or Slave  
• Commercial and Industrial Temperature Ranges  
• Available in 68-pin PLCC (all) and 64-pin TQFP  
(7C006AV & 7C144AV)  
— Active: ICC = 115 mA (typical)  
— Standby: ISB3 = 10 µA (typical)  
• Pin-compatible and functionally equivalent to  
IDT70V05, 70V06, and 70V07.  
Logic Block Diagram  
R/WL  
CEL  
R/WR  
CER  
OEL  
OER  
[1]  
[1]  
8/9  
8/9  
I/O0LI/O7/8L  
I/O0RI/O7/8R  
I/O  
Control  
I/O  
Control  
[2]  
1215  
1215  
[2]  
Address  
Decode  
Address  
Decode  
True Dual-Ported  
A0LA1114L  
A0RA1114R  
RAM Array  
1215  
1215  
[2]  
[2]  
A0LA1114L  
A0RA1114R  
CEL  
CER  
OER  
Interrupt  
Semaphore  
Arbitration  
OEL  
R/WL  
SEML  
R/WR  
SEMR  
[3]  
BUSYL  
INTL  
[3] BUSYR  
INTR  
M/S  
Notes:  
1. I/O0I/O7 for x8 devices; I/O0I/O8 for x9 devices.  
2. A0A11 for 4K devices; A0A12 for 8K devices; A0A13 for 16K devices; A0A14 for 32K devices;  
3. BUSY is an output in master mode and an input in slave mode.  
For the most recent information, visit the Cypress web site at www.cypress.com  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-06051 Rev. *A  
Revised December 27, 2002  

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