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CY7C1399V-35VC PDF预览

CY7C1399V-35VC

更新时间： 2024-11-26 23:45:27
品牌 Logo 应用领域
其他 - ETC 静态存储器
页数 文件大小 规格书
9页 174K
描述
x8 SRAM

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中文翻译

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CY7C1399V-35VC 数据手册

 浏览型号CY7C1399V-35VC的Datasheet PDF文件第2页浏览型号CY7C1399V-35VC的Datasheet PDF文件第3页浏览型号CY7C1399V-35VC的Datasheet PDF文件第4页浏览型号CY7C1399V-35VC的Datasheet PDF文件第5页浏览型号CY7C1399V-35VC的Datasheet PDF文件第6页浏览型号CY7C1399V-35VC的Datasheet PDF文件第7页 
CY7C1399V  
32K x 8 3.0V Static RAM  
pansion is provided by an active LOW chip enable (CE) and  
active LOW output enable (OE) and three-state drivers. The  
device has an automatic power-down feature, reducing the  
power consumption by more than 95% when deselected.  
Features  
• Single 3.0V power supply  
• Ideal for low-voltage cache memory applications  
• High speed  
An active LOW write enable signal (WE) controls the writ-  
ing/reading operation of the memory. When CE and WE inputs  
— 12/15 ns  
are both LOW, data on the eight data input/output pins (I/O  
0
• Low active power  
through I/O ) is written into the memory location addressed by  
7
— 198 mW (max.)  
the address present on the address pins (A through A ).  
0
14  
Reading the device is accomplished by selecting the device  
and enabling the outputs, CE and OE active LOW, while WE  
remains inactive or HIGH. Under these conditions, the con-  
tents of the location addressed by the information on address  
pins is present on the eight data input/output pins.  
• Low CMOS standby power (L)  
— 165 W (max.), f=f  
µ
MAX  
• 2.0V data retention (L)  
— 40 W (max.)  
µ
• Low-power alpha immune 6T cell  
• Plastic SOJ and TSOP packaging  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and write enable  
(WE) is HIGH. The CY7C1399V is available in standard  
300-mil-wide SOJ and 28-pin TSOP type I packages.  
Functional Description  
The CY7C1399V is a high-performance 3.0V CMOS static  
RAM organized as 32,768 words by 8 bits. Easy memory ex-  
Logic Block Diagram  
Pin Configurations  
SOJ  
Top View  
A
A
V
CC  
28  
27  
26  
1
2
3
4
5
6
5
6
WE  
A
A
7
A
4
8
25  
24  
A
3
A
9
A
2
A
A
A
A
23  
22  
10  
11  
12  
A
1
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
7
8
9
10  
11  
12  
13  
14  
OE  
A
0
0
1
2
3
4
5
6
21  
20  
INPUTBUFFER  
13  
CE  
I/O  
19  
18  
17  
A
14  
A
0
7
I/O  
I/O  
I/O  
I/O  
6
A
1
0
1
2
A
2
I/O  
5
16  
15  
A
3
I/O  
4
A
4
I/O  
3
GND  
A
A
A
A
A
32K x 8  
ARRAY  
5
6
7
8
9
C1399V-2  
CE  
WE  
POWER  
DOWN  
COLUMN  
DECODER  
I/O  
7
OE  
C1399V-1  
Selection Guide  
7C1399V 12 7C1399V 15 7C1399V 20 7C1399V 25 7C1399V 35  
−
−
−
−
−
Maximum Access Time (ns)  
12  
60  
15  
55  
20  
50  
25  
45  
35  
40  
Maximum Operating Current (mA)  
Maximum CMOS Standby Current (µA)  
500  
50  
500  
50  
500  
50  
500  
50  
500  
50  
Maximum CMOS Standby Current (µA)  
L
•
Shaded area contains advanced information.  
Cypress Semiconductor Corporation  
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
January 1996 - Revised June 1996  
1234567...9

中文翻译

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与CY7C1399V-35VC相关器件

型号 品牌 获取价格 描述 数据表
CY7C1399V-35ZC CYPRESS

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 		Cache SRAM, 32KX8, 35ns, CMOS, PDSO28, TSOP1-28
CY7C1399VL-12VC ETC

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 		x8 SRAM
CY7C1399VL-12ZC CYPRESS

获取价格

 		Cache SRAM, 32KX8, 12ns, CMOS, PDSO28, TSOP1-28
CY7C1399VL-15ZI CYPRESS

获取价格

 		Cache SRAM, 32KX8, 15ns, CMOS, PDSO28, TSOP1-28
CY7C1399VL-20VC CYPRESS

获取价格

 		Cache SRAM, 32KX8, 20ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28
CY7C1399VL-20ZC CYPRESS

获取价格

 		Cache SRAM, 32KX8, 20ns, CMOS, PDSO28, TSOP1-28
CY7C1399VL-25VC CYPRESS

获取价格

 		Cache SRAM, 32KX8, 25ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28
CY7C1399VL-25ZC CYPRESS

获取价格

 		Cache SRAM, 32KX8, 25ns, CMOS, PDSO28, TSOP1-28
CY7C1399VL-35VC CYPRESS

获取价格

 		Cache SRAM, 32KX8, 35ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28
CY7C1399VL-35ZC CYPRESS

获取价格

 		Cache SRAM, 32KX8, 35ns, CMOS, PDSO28, TSOP1-28

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