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CY7C1399V-20ZC PDF预览

CY7C1399V-20ZC

更新时间: 2024-11-27 20:26:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
9页 170K
描述
Cache SRAM, 32KX8, 20ns, CMOS, PDSO28, TSOP1-28

CY7C1399V-20ZC 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:TSOP
包装说明:TSOP1-28针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.92
Is Samacsys:N最长访问时间:20 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-G28
JESD-609代码:e0长度:11.8 mm
内存密度:262144 bit内存集成电路类型:CACHE SRAM
内存宽度:8湿度敏感等级:3
功能数量:1端口数量:1
端子数量:28字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32KX8输出特性:3-STATE
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:TSOP1封装等效代码:TSSOP28,.53,22
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:3 V认证状态:Not Qualified
座面最大高度:1.2 mm最大待机电流:0.0002 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.05 mA最大供电电压 (Vsup):3.3 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.55 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:8 mmBase Number Matches:1

CY7C1399V-20ZC 数据手册

 浏览型号CY7C1399V-20ZC的Datasheet PDF文件第2页浏览型号CY7C1399V-20ZC的Datasheet PDF文件第3页浏览型号CY7C1399V-20ZC的Datasheet PDF文件第4页浏览型号CY7C1399V-20ZC的Datasheet PDF文件第5页浏览型号CY7C1399V-20ZC的Datasheet PDF文件第6页浏览型号CY7C1399V-20ZC的Datasheet PDF文件第7页 
CY7C1399V  
32K x 8 3.0V Static RAM  
pansion is provided by an active LOW chip enable (CE) and  
active LOW output enable (OE) and three-state drivers. The  
device has an automatic power-down feature, reducing the  
power consumption by more than 95% when deselected.  
Features  
• Single 3.0V power supply  
• Ideal for low-voltage cache memory applications  
• High speed  
An active LOW write enable signal (WE) controls the writ-  
ing/reading operation of the memory. When CE and WE inputs  
— 12/15 ns  
are both LOW, data on the eight data input/output pins (I/O  
0
• Low active power  
through I/O ) is written into the memory location addressed by  
7
— 198 mW (max.)  
the address present on the address pins (A through A ).  
0
14  
Reading the device is accomplished by selecting the device  
and enabling the outputs, CE and OE active LOW, while WE  
remains inactive or HIGH. Under these conditions, the con-  
tents of the location addressed by the information on address  
pins is present on the eight data input/output pins.  
• Low CMOS standby power (L)  
— 165 W (max.), f=f  
µ
MAX  
• 2.0V data retention (L)  
— 40 W (max.)  
µ
• Low-power alpha immune 6T cell  
• Plastic SOJ and TSOP packaging  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and write enable  
(WE) is HIGH. The CY7C1399V is available in standard  
300-mil-wide SOJ and 28-pin TSOP type I packages.  
Functional Description  
The CY7C1399V is a high-performance 3.0V CMOS static  
RAM organized as 32,768 words by 8 bits. Easy memory ex-  
Logic Block Diagram  
Pin Configurations  
SOJ  
Top View  
A
A
V
CC  
28  
27  
26  
1
2
3
4
5
6
5
6
WE  
A
A
7
A
4
8
25  
24  
A
3
A
9
A
2
A
A
A
A
23  
22  
10  
11  
12  
A
1
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
7
8
9
10  
11  
12  
13  
14  
OE  
A
0
0
1
2
3
4
5
6
21  
20  
INPUTBUFFER  
13  
CE  
I/O  
19  
18  
17  
A
14  
A
0
7
I/O  
I/O  
I/O  
I/O  
6
A
1
0
1
2
A
2
I/O  
5
16  
15  
A
3
I/O  
4
A
4
I/O  
3
GND  
A
A
A
A
A
32K x 8  
ARRAY  
5
6
7
8
9
C1399V-2  
CE  
WE  
POWER  
DOWN  
COLUMN  
DECODER  
I/O  
7
OE  
C1399V-1  
Selection Guide  
7C1399V 12 7C1399V 15 7C1399V 20 7C1399V 25 7C1399V 35  
Maximum Access Time (ns)  
12  
60  
15  
55  
20  
50  
25  
45  
35  
40  
Maximum Operating Current (mA)  
Maximum CMOS Standby Current (µA)  
500  
50  
500  
50  
500  
50  
500  
50  
500  
50  
Maximum CMOS Standby Current (µA)  
L
Shaded area contains advanced information.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
January 1996 - Revised June 1996  

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