CY7C1395
CY7C1395V25
PRELIMINARY
2M x 36 PBSRAM with NoBL-Burst™ Architecture
Features
Functional Description
• Pin-compatible to ZBT™ and NoBL™ devices
• Supports up to166-MHz bus operations with zero wait
states
The CY7C1395V25 and CY7C1395 are 2.5V and 3.3V
2M × 36 synchronous pipelined burst SRAMs designed
specifically to support unlimited true back-to-back Read/Write
operations without the insertion of wait states. The
CY7C1395V25 operates with a 2.5V power supply and the
CY7C1395 operates with a 3.3V power supply. Both are
equipped with the advanced No Bus Latency-Burst™
(NoBL-Burst™) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of data through the SRAM, especially in systems that require
frequent Write/Read transitions.The CY7C1395V25 and
CY7C1395 are pin-compatible with ZBT and NoBL devices.
— Data is transferred on every clock
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Common I/O architecture
• Single 2.5V or 3.3V power supply
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 3.5 ns (166-MHz device).
— 4.2 ns (for 133-MHz device)
— 5.0 ns (for 100-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in 100 TQFP package
• 119 BGA package is offered by opportunity basis
(Check with Cypress sales and marketing)
• Burst Capability—linear or interleaved burst order
Write operations are controlled by the Byte Write Selects and
a Write Enable (WE) input. All writes are conducted with
on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Logic Block Diagram
D
CLK
Data-In REG.
CE
Q
ADV/LD
A[20:0]
2MX36
MEMORY
ARRAY
CEN
CE
CONTROL
and WRITE
LOGIC
1
CE
2
DQ[31:0]
DP[3:0]
CE
3
WE
BWS[a:d]
Mode
OE
Selection Guide
-166
-133
4.2
-100
5.0
Unit
ns
Maximum Access Time
3.5
220
20
Maximum Operating Current
200
20
175
20
mA
mA
Maximum CMOS Standby Current
Shaded area contains advanced information.
Cypress Semiconductor Corporation
Document #: 38-05183 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised February 19, 2003
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