Datasheet > 存储 > SRAM> CY7C139-25JCR

CY7C139-25JCR

更新时间： 2024-11-28 12:59:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器
页数	文件大小	规格书
16页	478K
描述
Dual-Port SRAM, 4KX9, 25ns, CMOS, PQCC68, PLASTIC, LCC-68

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技术参数
数据手册

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CY7C139-25JCR 技术参数

生命周期：	Obsolete	零件包装代码：	LCC
包装说明：	QCCJ,	针数：	68
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.41	风险等级：	5.84
Is Samacsys：	N	最长访问时间：	25 ns
其他特性：	SEMAPHORE	JESD-30 代码：	S-PQCC-J68
JESD-609代码：	e0	长度：	24.2316 mm
内存密度：	36864 bit	内存集成电路类型：	DUAL-PORT SRAM
内存宽度：	9	功能数量：	1
端口数量：	2	端子数量：	68
字数：	4096 words	字数代码：	4000
工作模式：	ASYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	4KX9
输出特性：	3-STATE	可输出：	YES
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
并行/串行：	PARALLEL	认证状态：	Not Qualified
座面最大高度：	5.08 mm	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN LEAD
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	宽度：	24.2316 mm
Base Number Matches：	1

CY7C139-25JCR 数据手册

CY7C138 CY7C1394K

with Sem, Int, Busy

x 8/9 Dual-Port Static RAM

CY7C138

CY7C139

4K x 8/9 Dual-Port Static RAM

with Sem, Int, Busy

are included on the CY7C138/9 to handle situations when

multiple processors access the same piece of data. Two ports

are provided permitting independent, asynchronous access

for reads and writes to any location in memory. The

CY7C138/9 can be utilized as a standalone 8/9-bit dual-port

static RAM or multiple devices can be combined in order to

function as a 16/18-bit or wider master/slave dual-port static

RAM. An M/S pin is provided for implementing 16/18-bit or

wider memory applications without the need for separate

master and slave devices or additional discrete logic. Appli-

cation areas include interprocessor/multiprocessor designs,

Features

• TrueDual-Portedmemorycellsthatallowsimultaneous

reads of the same memory location

• 4K x 8 organization (CY7C138)

• 4K x 9 organization (CY7C139)

• 0.65-micron CMOS for optimum speed/power

• High-speed access: 15 ns

• Low operating power: I_CC= 160 mA (max.)

• Fully asynchronous operation

• Automatic power-down

communications

status

buffering,

and

dual-port

video/graphics memory.

Each port has independent control pins: chip enable (CE),

read or write enable (R/W), and output enable (OE). Two flags

are provided on each port (BUSY and INT). BUSY signals that

the port is trying to access the same location currently being

accessed by the other port. The interrupt flag (INT) permits

communication between ports or systems by means of a mail

box. The semaphores are used to pass a flag, or token, from

one port to the other to indicate that a shared resource is in

use. The semaphore logic is comprised of eight shared

latches. Only one side can control the latch (semaphore) at

any time. Control of a semaphore indicates that a shared

resource is in use. An automatic power-down feature is

controlled independently on each port by a chip enable (CE)

pin or SEM pin.

• TTL compatible

• Expandable data bus to 32/36 bits or more using

Master/Slave chip select when using more than one

device

• On-chip arbitration logic

• Semaphores included to permit software handshaking

between ports

• INT flag for port-to-port communication

• Available in 68-pin PLCC

• Pb-Free packages available

Functional Description

The CY7C138 and CY7C139 are available in a 68-pin PLCC.

The CY7C138 and CY7C139 are high-speed CMOS 4K x 8

and 4K x 9 dual-port static RAMs. Various arbitration schemes

Logic BlockDiagram

R/W

I/O

(7C139)

BUSY

I/O (7C139)

I/O

CONTROL

I/O

CONTROL

I/O

[1, 2]

BUSY

11L

11R

ADDRESS

DECODER

ADDRESS

DECODER

MEMORY

ARRAY

INTERRUPT

SEMAPHORE

ARBITRATION

R/W

SEM

[2]

INT

M/S

Notes:

1. BUSY is an output in master mode and an input in slave mode.

2. Interrupt: push-pull output and requires no pull-up resistor.

Cypress Semiconductor Corporation

Document #: 38-06037 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 6, 2005

12 3 4 5 6 7...16

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与CY7C139-25JCR相关器件

型号	品牌	获取价格	描述	数据表
CY7C139-25JCT	CYPRESS	获取价格	Dual-Port SRAM, 4KX9, 25ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C139-25JI	CYPRESS	获取价格	4K x 8/9 Dual-Port Static RAM
CY7C139-25JXC	CYPRESS	获取价格	4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
CY7C1392AV18	CYPRESS	获取价格	18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1392AV18-167BZC	CYPRESS	获取价格	18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1392AV18-200BZC	CYPRESS	获取价格	18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1392AV18-250BZC	CYPRESS	获取价格	18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1392BV18	CYPRESS	获取价格	RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
CY7C1392BV18-167BZC	CYPRESS	获取价格	18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1392BV18-167BZI	CYPRESS	获取价格	18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

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