Datasheet > CY7C1387FV25-250BGXC

CY7C1387FV25-250BGXC

更新时间： 2024-11-28 09:44:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
30页	1165K
描述
18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM

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CY7C1387FV25-250BGXC 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	BGA,
针数：	119	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.84	Base Number Matches：	1

CY7C1387FV25-250BGXC 数据手册

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CY7C1386DV25, CY7C1386FV25

CY7C1387DV25, CY7C1387FV25

18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM

Features

Functional Description ^[1]

• Supports bus operation up to 250 MHz

The

CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/

CY7C1387FV25 SRAM integrates 512K x 36 and 1M x 18

SRAM cells with advanced synchronous peripheral circuitry

and a two-bit counter for internal burst operation. All

synchronous inputs are gated by registers controlled by a

positive edge triggered clock input (CLK). The synchronous

inputs include all addresses, all data inputs, address-pipelining

chip enable (CE₁), depth expansion chip enables (CE₂and

CE₃^[2]), burst control inputs (ADSC, ADSP, and ADV), write

enables (BW_X, and BWE), and global write (GW).

Asynchronous inputs include the output enable (OE) and the

ZZ pin.

• Available speed grades are 250, 200, and 167 MHz

• Registered inputs and outputs for pipelined operation

• Optimal for performance (Double-Cycle deselect)

• Depth expansion without wait state

• 2.5V + 5% power supply (V_DD

)

• Fast clock-to-output times, 2.6 ns (for 250 MHz device)

• Provides high-performance 3-1-1-1 access rate

• User selectable burst counter supporting Intel^®Pentium^®

interleaved or linear burst sequences

Addresses and chip enables are registered at rising edge of

clock when either address strobe processor (ADSP) or

address strobe controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the advance pin (ADV).

• Separate processor and controller address strobes

• Synchronous self timed writes

• Asynchronous output enable

• CY7C1386DV25/CY7C1387DV25 available in

JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non

Pb-free 165-ball FBGA package.

CY7C1386FV25/CY7C1387FV25 available in Pb-free and

non Pb-free 119-ball BGA package

Address, data inputs, and write controls are registered on-chip

to initiate a self timed write cycle.This part supports byte write

operations (see Pin Definitions on page 6 and Truth Table ^[4,

5, 6, 7, 8, 9]

on page 9 for further details). Write cycles can be

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• ZZ sleep mode option

one to four bytes wide as controlled by the byte write control

inputs. GW

This

causes all bytes to be written.

active

LOW

device incorporates an additional pipelined enable register

which delays turning off the output buffers an additional cycle

when a deselect is executed.This feature allows depth

expansion without penalizing system performance.

The

CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/

CY7C1387FV25 operates from a +2.5V power supply. All

inputs

and

outputs

are

JEDEC-standard

and

JESD8-5-compatible.

Selection Guide

250 MHz

200 MHz

3.0

167 MHz

3.4

Unit

Maximum Access Time

2.6

350

Maximum Operating Current

Maximum CMOS Standby Current

300

275

Notes

1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.

2. CE CE are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.

Cypress Semiconductor Corporation

Document Number: 38-05548 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised Feburary 15, 2007

12 3 4 5 6 7...30

中文翻译

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与CY7C1387FV25-250BGXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1387FV25-250BGXI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1387KV33	CYPRESS	获取价格	18-Mbit (512K Ã 36/1M Ã 18) Pipelined DCD S
CY7C1387KV33-167AXC	CYPRESS	获取价格	18-Mbit (512K Ã 36/1M Ã 18) Pipelined DCD S
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