Datasheet > CY7C1387F

CY7C1387F

更新时间： 2024-11-25 09:44:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
36页	1183K
描述
18-Mbit (512 K x 36/1 M x 18) Pipelined DCD Sync SRAM

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CY7C1387F 数据手册

CY7C1386D, CY7C1386F

CY7C1387D, CY7C1387F

18-Mbit (512 K × 36/1 M × 18) Pipelined

DCD Sync SRAM

18-Mbit (512

K × 36/1 M × 18) Pipelined DCD Sync SRAM

Features

Functional Description

■ Supports bus operation up to 250 MHz

The

CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F

SRAM^[1]integrates 512 K × 36/1 M × 18 SRAM cells with

advanced synchronous peripheral circuitry and a two-bit counter

for internal burst operation. All synchronous inputs are gated by

registers controlled by a positive edge triggered clock input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining chip enable (CE₁), depth expansion

chip enables (CE₂and CE₃^[2]), burst control inputs (ADSC,

■ Available speed grades are 250, 200, and 167 MHz

■ Registered inputs and outputs for pipelined operation

■ Optimal for performance (double-cycle deselect)

■ Depth expansion without wait state

■ 3.3 V core power supply (V_DD

)

ADSP,

ADV), write enables (

, and BWE), and global

BW_X

and

write (GW). Asynchronous inputs include the output enable (OE)

and the ZZ pin.

■ 2.5 V or 3.3 V I/O power supply (V_DDQ)

■ Fast clock-to-output times

❐ 2.6 ns (for 250 MHz device)

Addresses and chip enables are registered at rising edge of

clock when either address strobe processor (ADSP) or address

strobe controller (ADSC) are active. Subsequent burst

addresses can be internally generated as controlled by the

advance pin (ADV).

■ Provides high performance 3-1-1-1 access rate

■ User selectable burst counter supporting Intel^ Pentium^

Interleaved or linear burst sequences

Address, data inputs, and write controls are registered on-chip

to initiate a self timed write cycle.This part supports byte write

operations (see on page 4 and Truth Table on page 11 for further

details). Write cycles can be one to four bytes wide as controlled

by the byte write control inputs. GW active LOW causes all bytes

to be written. This device incorporates an additional pipelined

enable register which delays turning off the output buffers an

additional cycle when a deselect is executed.This feature allows

depth expansion without penalizing system performance.

■ Separate processor and controller address strobes

■ Synchronous self-timed writes

■ Asynchronous output enable

■ CY7C1386D/CY7C1387D available in JEDEC-standard

Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA

package. CY7C1386F/CY7C1387F available in Pb-free and

non Pb-free 119-ball BGA package

The

CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F

■ IEEE 1149.1 JTAG-compatible boundary scan

■ ZZ sleep mode option

operates from a +3.3 V core power supply while all outputs

operate with a +3.3 V or +2.5 V supply. All inputs and outputs are

JEDEC-standard and JESD8-5-compatible.

Selection Guide

Description

Maximum access time

250 MHz

2.6

200 MHz

3.0

167 MHz

3.4

Unit

Maximum operating current

350

300

275

Maximum CMOS standby current

Notes

1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.

2. CE and CE are for 100-pin TQFP and 165-ball FBGA packages only. 119-ball BGA is offered only in Single Chip Enable.

Cypress Semiconductor Corporation

Document Number: 38-05545 Rev. *H

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 12, 2011

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与CY7C1387F相关器件

型号	品牌	获取价格	描述	数据表
CY7C1387F-167BGC	CYPRESS	获取价格	18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
CY7C1387F-167BGI	CYPRESS	获取价格	18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
CY7C1387F-167BGXC	CYPRESS	获取价格	18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
CY7C1387F-167BGXI	CYPRESS	获取价格	18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
CY7C1387F-200BGC	CYPRESS	获取价格	18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
CY7C1387F-200BGI	CYPRESS	获取价格	18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
CY7C1387F-200BGXC	CYPRESS	获取价格	18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
CY7C1387F-200BGXI	CYPRESS	获取价格	18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
CY7C1387F-250BGC	CYPRESS	获取价格	18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
CY7C1387F-250BGI	CYPRESS	获取价格	18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM

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