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CY7C1387DV25-167BGXI PDF预览

CY7C1387DV25-167BGXI

更新时间： 2024-11-26 10:00:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
29页 536K
描述
Cache SRAM, 1MX18, 3.4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119

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CY7C1387DV25-167BGXI 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119针数：119
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.84
最长访问时间：3.4 ns其他特性：PIPELINED ARCHITECTURE
JESD-30 代码：R-PBGA-B119JESD-609代码：e1
长度：22 mm内存密度：18874368 bit
内存集成电路类型：CACHE SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：119字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：1MX18封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：2.4 mm最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：20
宽度：14 mm

CY7C1387DV25-167BGXI 数据手册

 浏览型号CY7C1387DV25-167BGXI的Datasheet PDF文件第2页浏览型号CY7C1387DV25-167BGXI的Datasheet PDF文件第3页浏览型号CY7C1387DV25-167BGXI的Datasheet PDF文件第4页浏览型号CY7C1387DV25-167BGXI的Datasheet PDF文件第5页浏览型号CY7C1387DV25-167BGXI的Datasheet PDF文件第6页浏览型号CY7C1387DV25-167BGXI的Datasheet PDF文件第7页 
CY7C1386DV25  
CY7C1387DV25  
18-Mbit (512K x 36/1M x 18)  
Pipelined DCD Sync SRAM  
Functional Description[1]  
Features  
• Supports bus operation up to 250 MHz  
The CY7C1386DV25/CY7C1387DV25 SRAM integrates  
512K x 36 and 1M x 18 SRAM cells with advanced  
synchronous peripheral circuitry and a two-bit counter for  
internal burst operation. All synchronous inputs are gated by  
registers controlled by a positive-edge-triggered Clock Input  
(CLK). The synchronous inputs include all addresses, all data  
• Available speed grades are 250, 200 and 167 MHz  
• Registered inputs and outputs for pipelined operation  
• Optimal for performance (Double-Cycle deselect)  
• Depth expansion without wait state  
inputs,  
address-pipelining  
Chip  
Enable  
(CE1),  
• 2.5V + 5% power supply (VDD  
)
depth-expansion Chip Enables (CE2 and CE3[2]), Burst  
Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX,  
and BWE), and Global Write (GW). Asynchronous inputs  
include the Output Enable (OE) and the ZZ pin.  
• Fast clock-to-output times  
— 2.6 ns (for 250-MHz device)  
• Provide high-performance 3-1-1-1 access rate  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (ADSP) or  
Address Strobe Controller (ADSC) are active. Subsequent  
burst addresses can be internally generated as controlled by  
the Advance pin (ADV).  
• User-selectable burst counter supporting Intel®  
Pentium® interleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self-timed writes  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed Write cycle.This part supports Byte Write  
operations (see Pin Descriptions and Truth Table for further  
details). Write cycles can be one to four bytes wide as  
• Asynchronous output enable  
• Available in JEDEC-standard lead-free 100-pin TQFP,  
lead-free and non-lead-free 119-Ball BGA and 165-Ball  
FBGA packages  
controlled by the byte write control inputs. GW  
active  
LOW  
This device incorporates an  
causes all bytes to be written.  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• “ZZ” Sleep Mode Option  
additional pipelined enable register which delays turning off  
the output buffers an additional cycle when a deselect is  
executed.This feature allows depth expansion without penal-  
izing system performance.  
The CY7C1386DV25/CY7C1387DV25 operates from a +2.5V  
power supply. All inputs and outputs are JEDEC-standard  
JESD8-5-compatible.  
Selection Guide  
250 MHz  
2.6  
200 MHz  
3.0  
167 MHz  
3.4  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
350  
300  
275  
mA  
mA  
70  
70  
70  
Notes:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
2. CE and CE are for TQFP and 165 FBGA package only. 119 BGA is offered only in Single Chip Enable.  
3
2
Cypress Semiconductor Corporation  
Document #: 38-05548 Rev. *D  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised June 28, 2006  
1234567...29

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CY7C1387DV25-167BZC CYPRESS

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 		18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1387DV25-167BZI CYPRESS

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 		18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1387DV25-167BZXC CYPRESS

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 		18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1387DV25-167BZXI CYPRESS

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 		18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1387DV25-200AC CYPRESS

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 		Cache SRAM, 1MX18, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1387DV25-200AI CYPRESS

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 		Cache SRAM, 1MX18, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1387DV25-200AXC CYPRESS

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 		18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1387DV25-200AXI CYPRESS

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 		18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1387DV25-200BGI CYPRESS

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 		Cache SRAM, 1MX18, 3ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
CY7C1387DV25-200BGXI CYPRESS

获取价格

 		Cache SRAM, 1MX18, 3ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119

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