Datasheet > 存储 > SRAM> CY7C1387D-200AXI

CY7C1387D-200AXI

更新时间： 2024-11-25 03:11:03

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
30页	1241K
描述
18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM

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数据手册

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CY7C1387D-200AXI 数据手册

CY7C1386D, CY7C1386F

CY7C1387D, CY7C1387F

18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM

Features

Functional Description ^[1]

• Supports bus operation up to 250 MHz

The

CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F

SRAM integrates 512K x 36/1M x 18 SRAM cells with

advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive edge triggered clock

input (CLK). The synchronous inputs include all addresses, all

data inputs, address-pipelining chip enable (CE₁), depth

expansion chip enables (CE₂and CE₃^[2]), burst control inputs

• Available speed grades are 250, 200, and 167 MHz

• Registered inputs and outputs for pipelined operation

• Optimal for performance (double-cycle deselect)

• Depth expansion without wait state

• 3.3V core power supply (V_DD

)

• 2.5V or 3.3V IO power supply (V_DDQ)

• Fast clock-to-output times

(ADSC, ADSP,

ADV), write enables ( , and BWE), and

BW_X

and

global write (GW). Asynchronous inputs include the output

enable (OE) and the ZZ pin.

— 2.6 ns (for 250 MHz device)

Addresses and chip enables are registered at rising edge of

clock when either address strobe processor (ADSP) or

address strobe controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the advance pin (ADV).

• Provides high-performance 3-1-1-1 access rate

• User selectable burst counter supporting Intel^®Pentium^®

interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self timed writes

Address, data inputs, and write controls are registered on-chip

to initiate a self timed write cycle.This part supports byte write

operations (see Pin Configurations on page 3 and Truth Table

^{[4, 5, 6, 7, 8]}on page 9 for further details). Write cycles can be

one to four bytes wide as controlled by the byte write control

inputs. GW active LOW causes all bytes to be written. This

device incorporates an additional pipelined enable register

which delays turning off the output buffers an additional cycle

when a deselect is executed.This feature allows depth

expansion without penalizing system performance.

• Asynchronous output enable

• CY7C1386D/CY7C1387D available in JEDEC-standard

Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball

FBGA package. CY7C1386F/CY7C1387F available in

Pb-free and non Pb-free 119-ball BGA package

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• ZZ sleep mode option

The

CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F

operates from a +3.3V core power supply while all outputs

operate with a +3.3V or +2.5V supply. All inputs and outputs

are JEDEC-standard and JESD8-5-compatible.

Selection Guide

250 MHz

200 MHz

3.0

167 MHz

3.4

Unit

Maximum Access Time

2.6

350

Maximum Operating Current

Maximum CMOS Standby Current

300

275

Notes

1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.

2. CE and CE are for TQFP and 165 FBGA packages only. 119 BGA is offered only in Single Chip Enable.

Cypress Semiconductor Corporation

Document Number: 38-05545 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised Feburary 09, 2007

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与CY7C1387D-200AXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1387D-200BGC	CYPRESS	获取价格	18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
CY7C1387D-200BGCT	CYPRESS	获取价格	Cache SRAM, 1MX18, 3ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
CY7C1387D-200BGI	CYPRESS	获取价格	18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
CY7C1387D-200BGXC	CYPRESS	获取价格	18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
CY7C1387D-200BGXI	CYPRESS	获取价格	18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
CY7C1387D-200BZC	CYPRESS	获取价格	18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
CY7C1387D-200BZI	CYPRESS	获取价格	18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
CY7C1387D-200BZXC	CYPRESS	获取价格	18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
CY7C1387D-200BZXI	CYPRESS	获取价格	18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
CY7C1387D-225AI	CYPRESS	获取价格	Cache SRAM, 1MX18, 2.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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