CY7C1387CV25-225AI

更新时间： 2024-11-25 05:19:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
36页	548K
描述
18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM

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CY7C1387CV25-225AI 数据手册

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CY7C1386CV25

CY7C1387CV25

18-Mb (512K x 36/1M x 18) Pipelined DCD

Sync SRAM

Features

Functional Description^[1]

• Supports bus operation up to 250 MHz

The CY7C1386CV25/CY7C1387CV25 SRAM integrates

524,288 x 36 and 1048,576 x 18 SRAM cells with advanced

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. All synchronous inputs are gated by

registers controlled by a positive-edge-triggered Clock Input

(CLK). The synchronous inputs include all addresses, all data

• Available speed grades are 250, 225, 200 and 167 MHz

• Registered inputs and outputs for pipelined operation

• Optimal for performance (Double-Cycle deselect)

• Depth expansion without wait state

inputs,

address-pipelining

Chip

Enable _[2]

(

CE₁

• 2.5V + 5% power supply (V_DD

)

depth-expansion Chip Enables (CE₂and

CE₃

), Burst

Control inputs (

), Write Enables (

and

BW_X

ADV

ADSC ADSP

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

— 2.8 ns (for 225-MHz device)

— 3.0 ns (for 200-MHz device)

— 3.4 ns (for 167-MHz device)

and

), and Global Write (

). Asynchronous inputs

BWE

include the Output Enable ( ) and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (

) or

ADSP

Address Strobe Controller (

) are active. Subsequent

ADSC

burst addresses can be internally generated as controlled by

the Advance pin ( ).

• Provide high-performance 3-1-1-1 access rate

ADV

• User-selectable burst counter supporting Intel^

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to four bytes wide as

Pentium interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

controlled by the byte write control inputs.

active

LOW

This device incorporates an

causes all bytes to be written.

additional pipelined enable register which delays turning off

the output buffers an additional cycle when a deselect is

executed.This feature allows depth expansion without penal-

izing system performance.

• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA

and 165-Ball fBGA packages

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

The CY7C1386CV25/CY7C1387CV25 operates from a +2.5V

power supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Selection Guide

250 MHz

225 MHz

2.8

200 MHz

3.0

167 MHz

3.4

Unit

Maximum Access Time

Maximum Operating Current

2.6

350

325

300

275

Maximum CMOS Standby Current

Shaded areas contain advance information.

Please contact your local Cypress sales representative for availability of these parts.

Notes:

1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE and CE are for TQFP and 165 fBGA package only. 119 BGA is offered only in Single Chip Enable.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05242 Rev. *A

Revised February 26, 2004

12 3 4 5 6 7...36

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与CY7C1387CV25-225AI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1387CV25-225BGC	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1387CV25-225BGI	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1387CV25-225BZC	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1387CV25-225BZI	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1387CV25-250AC	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1387CV25-250AI	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1387CV25-250BGC	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1387CV25-250BGI	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1387CV25-250BZC	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1387D	CYPRESS	获取价格	18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM

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