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CY7C1387CV25-200BGI PDF预览

CY7C1387CV25-200BGI

更新时间： 2024-11-25 05:19:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
36页 548K
描述
18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM

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CY7C1387CV25-200BGI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119针数：119
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.92
最长访问时间：3 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：200 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B119JESD-609代码：e0
长度：22 mm内存密度：18874368 bit
内存集成电路类型：CACHE SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：119字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：1MX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA119,7X17,50封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：220电源：2.5 V
认证状态：Not Qualified座面最大高度：2.4 mm
最大待机电流：0.03 A最小待机电流：2.38 V
子类别：SRAMs最大压摆率：0.22 mA
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

CY7C1387CV25-200BGI 数据手册

 浏览型号CY7C1387CV25-200BGI的Datasheet PDF文件第2页浏览型号CY7C1387CV25-200BGI的Datasheet PDF文件第3页浏览型号CY7C1387CV25-200BGI的Datasheet PDF文件第4页浏览型号CY7C1387CV25-200BGI的Datasheet PDF文件第5页浏览型号CY7C1387CV25-200BGI的Datasheet PDF文件第6页浏览型号CY7C1387CV25-200BGI的Datasheet PDF文件第7页 
CY7C1386CV25  
CY7C1387CV25  
18-Mb (512K x 36/1M x 18) Pipelined DCD  
Sync SRAM  
Features  
Functional Description[1]  
• Supports bus operation up to 250 MHz  
The CY7C1386CV25/CY7C1387CV25 SRAM integrates  
524,288 x 36 and 1048,576 x 18 SRAM cells with advanced  
synchronous peripheral circuitry and a two-bit counter for  
internal burst operation. All synchronous inputs are gated by  
registers controlled by a positive-edge-triggered Clock Input  
(CLK). The synchronous inputs include all addresses, all data  
• Available speed grades are 250, 225, 200 and 167 MHz  
• Registered inputs and outputs for pipelined operation  
• Optimal for performance (Double-Cycle deselect)  
• Depth expansion without wait state  
inputs,  
address-pipelining  
Chip  
Enable [2]  
(
),  
CE1  
• 2.5V + 5% power supply (VDD  
)
depth-expansion Chip Enables (CE2 and  
CE3  
), Burst  
Control inputs (  
,
,
), Write Enables (  
,
and  
BWX  
ADV  
ADSC ADSP  
• Fast clock-to-output times  
— 2.6 ns (for 250-MHz device)  
— 2.8 ns (for 225-MHz device)  
— 3.0 ns (for 200-MHz device)  
— 3.4 ns (for 167-MHz device)  
and  
), and Global Write (  
GW  
). Asynchronous inputs  
BWE  
include the Output Enable ( ) and the ZZ pin.  
OE  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (  
) or  
ADSP  
Address Strobe Controller (  
) are active. Subsequent  
ADSC  
burst addresses can be internally generated as controlled by  
the Advance pin ( ).  
• Provide high-performance 3-1-1-1 access rate  
ADV  
• User-selectable burst counter supporting Intel  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed Write cycle.This part supports Byte Write  
operations (see Pin Descriptions and Truth Table for further  
details). Write cycles can be one to four bytes wide as  
Pentium interleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self-timed writes  
• Asynchronous output enable  
controlled by the byte write control inputs.  
active  
GW  
LOW  
This device incorporates an  
causes all bytes to be written.  
additional pipelined enable register which delays turning off  
the output buffers an additional cycle when a deselect is  
executed.This feature allows depth expansion without penal-  
izing system performance.  
• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA  
and 165-Ball fBGA packages  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• “ZZ” Sleep Mode Option  
The CY7C1386CV25/CY7C1387CV25 operates from a +2.5V  
power supply. All inputs and outputs are JEDEC-standard  
JESD8-5-compatible.  
Selection Guide  
250 MHz  
225 MHz  
2.8  
200 MHz  
3.0  
167 MHz  
3.4  
Unit  
ns  
mA  
mA  
Maximum Access Time  
Maximum Operating Current  
2.6  
350  
70  
325  
70  
300  
70  
275  
70  
Maximum CMOS Standby Current  
Shaded areas contain advance information.  
Please contact your local Cypress sales representative for availability of these parts.  
Notes:  
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
2. CE and CE are for TQFP and 165 fBGA package only. 119 BGA is offered only in Single Chip Enable.  
3
2
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05242 Rev. *A  
Revised February 26, 2004  
1234567...36

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