5秒后页面跳转
捷配首页

Datasheet > 存储 > SRAM> CY7C1386DV25-250BZC
CY7C1386DV25-250BZC PDF预览

CY7C1386DV25-250BZC

更新时间： 2024-02-13 11:44:29
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
30页 1165K
描述
18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM

阅读下载

获取价格

CY7C1386DV25-250BZC 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：LBGA,针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.84
最长访问时间：2.6 ns其他特性：PIPELINED ARCHITECTURE
JESD-30 代码：R-PBGA-B165JESD-609代码：e1
长度：15 mm内存密度：18874368 bit
内存集成电路类型：CACHE SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端子数量：165字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：512KX36封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.4 mm最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：20
宽度：13 mmBase Number Matches：1

CY7C1386DV25-250BZC 数据手册

 浏览型号CY7C1386DV25-250BZC的Datasheet PDF文件第2页浏览型号CY7C1386DV25-250BZC的Datasheet PDF文件第3页浏览型号CY7C1386DV25-250BZC的Datasheet PDF文件第4页浏览型号CY7C1386DV25-250BZC的Datasheet PDF文件第5页浏览型号CY7C1386DV25-250BZC的Datasheet PDF文件第6页浏览型号CY7C1386DV25-250BZC的Datasheet PDF文件第7页 
CY7C1386DV25, CY7C1386FV25  
CY7C1387DV25, CY7C1387FV25  
18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM  
Features  
Functional Description [1]  
• Supports bus operation up to 250 MHz  
The  
CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/  
CY7C1387FV25 SRAM integrates 512K x 36 and 1M x 18  
SRAM cells with advanced synchronous peripheral circuitry  
and a two-bit counter for internal burst operation. All  
synchronous inputs are gated by registers controlled by a  
positive edge triggered clock input (CLK). The synchronous  
inputs include all addresses, all data inputs, address-pipelining  
chip enable (CE1), depth expansion chip enables (CE2 and  
CE3 [2]), burst control inputs (ADSC, ADSP, and ADV), write  
enables (BWX, and BWE), and global write (GW).  
Asynchronous inputs include the output enable (OE) and the  
ZZ pin.  
• Available speed grades are 250, 200, and 167 MHz  
• Registered inputs and outputs for pipelined operation  
• Optimal for performance (Double-Cycle deselect)  
• Depth expansion without wait state  
• 2.5V + 5% power supply (VDD  
)
• Fast clock-to-output times, 2.6 ns (for 250 MHz device)  
• Provides high-performance 3-1-1-1 access rate  
• User selectable burst counter supporting Intel® Pentium®  
interleaved or linear burst sequences  
Addresses and chip enables are registered at rising edge of  
clock when either address strobe processor (ADSP) or  
address strobe controller (ADSC) are active. Subsequent  
burst addresses can be internally generated as controlled by  
the advance pin (ADV).  
• Separate processor and controller address strobes  
• Synchronous self timed writes  
• Asynchronous output enable  
• CY7C1386DV25/CY7C1387DV25 available in  
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non  
Pb-free 165-ball FBGA package.  
CY7C1386FV25/CY7C1387FV25 available in Pb-free and  
non Pb-free 119-ball BGA package  
Address, data inputs, and write controls are registered on-chip  
to initiate a self timed write cycle.This part supports byte write  
operations (see Pin Definitions on page 6 and Truth Table [4,  
5, 6, 7, 8, 9]  
on page 9 for further details). Write cycles can be  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• ZZ sleep mode option  
one to four bytes wide as controlled by the byte write control  
inputs. GW  
This  
causes all bytes to be written.  
active  
LOW  
device incorporates an additional pipelined enable register  
which delays turning off the output buffers an additional cycle  
when a deselect is executed.This feature allows depth  
expansion without penalizing system performance.  
The  
CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/  
CY7C1387FV25 operates from a +2.5V power supply. All  
inputs  
and  
outputs  
are  
JEDEC-standard  
and  
JESD8-5-compatible.  
Selection Guide  
250 MHz  
200 MHz  
3.0  
167 MHz  
3.4  
Unit  
ns  
Maximum Access Time  
2.6  
350  
70  
Maximum Operating Current  
Maximum CMOS Standby Current  
300  
275  
mA  
mA  
70  
70  
Notes  
1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.  
2. CE CE are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.  
3,  
2
Cypress Semiconductor Corporation  
Document Number: 38-05548 Rev. *E  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised Feburary 15, 2007  
1234567...30

下载PDF

与CY7C1386DV25-250BZC相关器件

型号 品牌 描述 获取价格 数据表
CY7C1386DV25-250BZI CYPRESS 18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM

获取价格
CY7C1386DV25-250BZXC CYPRESS 18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM

获取价格
CY7C1386DV25-250BZXI CYPRESS 18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM

获取价格
CY7C1386F CYPRESS 18-Mbit (512 K x 36/1 M x 18) Pipelined DCD Sync SRAM

获取价格
CY7C1386F-167BGC CYPRESS 18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM

获取价格
CY7C1386F-167BGI CYPRESS 18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM

获取价格

与CY7C1386DV25-250BZC相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证