Datasheet > CY7C1383KVE33-133AXI

CY7C1383KVE33-133AXI

更新时间： 2024-11-06 14:56:11

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
34页	1114K
描述
Synchronous SRAM with ECC

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CY7C1381KV33/CY7C1381KVE33

CY7C1383KV33/CY7C1383KVE33

18-Mbit (512K × 36/1M × 18)

Flow-Through SRAM (With ECC)

18-Mbit (512K

× 36/1M × 18) Flow-Through SRAM (With ECC)

Features

Functional Description

■ Supports 133 MHz bus operations

■ 512K × 36 and 1M × 18 common I/O

The CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/

CY7C1383KVE33 are a 3.3 V, 512K × 36 and 1M × 18

synchronous flow through SRAMs, designed to interface with

high speed microprocessors with minimum glue logic. Maximum

access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit

on-chip counter captures the first address in a burst and

increments the address automatically for the rest of the burst

access. All synchronous inputs are gated by registers controlled

by a positive edge triggered clock input (CLK). The synchronous

inputs include all addresses, all data inputs, address pipelining

chip enable (CE₁), depth-expansion chip enables (CE₂and

CE₃), burst control inputs (ADSC, ADSP, and ADV), write

enables (BW_x, and BWE), and global write (GW). Asynchronous

inputs include the output enable (OE) and the ZZ pin.

■ 3.3 V core power supply (V_DD

)

■ 2.5 V or 3.3 V I/O supply (V_DDQ

)

■ Fast clock-to-output time

❐ 6.5 ns (133 MHz version)

■ Provides high performance 2-1-1-1 access rate

■ User selectable burst counter supporting interleaved or linear

burst sequences

■ Separate processor and controller address strobes

■ Synchronous self-timed write

CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/

The

CY7C1383KVE33

allows interleaved or linear burst sequences,

selected by the MODE input pin. A HIGH selects an interleaved

burst sequence, while a LOW selects a linear burst sequence.

Burst accesses can be initiated with the processor address

strobe (ADSP) or the cache controller address strobe (ADSC)

inputs. Address advancement is controlled by the address

advancement (ADV) input.

■ Asynchronous output enable

■ CY7C1381KV33/CY7C1381KVE33

available

JEDEC-standard Pb-free 100-pin TQFP, Pb-free 165-ball

FBGA package. CY7C1383KV33/CY7C1383KVE33 available

in JEDEC-standard Pb-free 100-pin TQFP.

Addresses and chip enables are registered at rising edge of

clock when address strobe processor (ADSP) or address strobe

controller (ADSC) are active. Subsequent burst addresses can

be internally generated as controlled by the advance pin (ADV).

■ IEEE 1149.1 JTAG-Compatible Boundary Scan

■ ZZ sleep mode option.

CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/

■ On-chip error correction code (ECC) to reduce soft error rate

(SER)

CY7C1383KVE33 operates from a +3.3 V core power supply

while all outputs operate with a +2.5 V or +3.3 V supply. All inputs

and outputs are JEDEC-standard and JESD8-5-compatible.

Selection Guide

Description

Maximum access time

133 MHz

6.5

100 MHz Unit

8.5

114

134

Maximum operating current

× 18

× 36

129

149

Cypress Semiconductor Corporation

Document Number: 001-97888 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 16, 2018

12 3 4 5 6 7...34

中文翻译

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与CY7C1383KVE33-133AXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1384D	CYPRESS	获取价格	18-Mbit (512 K Ã 32) Pipelined SRAM
CY7C1384D-166AXI	CYPRESS	获取价格	18-Mbit (512 K Ã 32) Pipelined SRAM
CY7C138-55	CYPRESS	获取价格	4K x 8/9 Dual-Port Static RAM
CY7C138-55JC	CYPRESS	获取价格	4K x 8/9 Dual-Port Static RAM
CY7C138-55JCT	CYPRESS	获取价格	Dual-Port SRAM, 4KX8, 55ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C138-55JI	CYPRESS	获取价格	4K x 8/9 Dual-Port Static RAM
CY7C138-55JIT	CYPRESS	获取价格	Dual-Port SRAM, 4KX8, 55ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C1385D	CYPRESS	获取价格	18-Mbit (512 K Ã 32) Flow-Through SRAM
CY7C1385D-133AXI	CYPRESS	获取价格	18-Mbit (512 K Ã 32) Flow-Through SRAM
CY7C1386B	CYPRESS	获取价格	512K x 36/1M x 18 Pipelined DCD SRAM

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