Datasheet > CY7C1383DV25-100AI

CY7C1383DV25-100AI

更新时间： 2024-09-25 15:30:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器内存集成电路
页数	文件大小	规格书
29页	500K
描述
Cache SRAM, 1MX18, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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CY7C1383DV25-100AI 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP,	针数：	100
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.92
最长访问时间：	8.5 ns	其他特性：	FLOW-THROUGH ARCHITECTURE
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
长度：	20 mm	内存密度：	18874368 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	18
湿度敏感等级：	3	功能数量：	1
端子数量：	100	字数：	1048576 words
字数代码：	1000000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	1MX18	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	225	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大供电电压 (Vsup)：	2.625 V
最小供电电压 (Vsup)：	2.375 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	TIN LEAD (800)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	14 mm	Base Number Matches：	1

CY7C1383DV25-100AI 数据手册

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CY7C1381DV25

CY7C1383DV25

PRELIMINARY

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Features

Functional Description^[1]

• Supports 133-MHz bus operations

• 512K x 36/1M x 18 common I/O

• 2.5V –5% and +10% core power supply (V_DD

The CY7C1381DV25/CY7C1383DV25 are 2.5V, 512K x 36

and 1M x 18 Synchronous Flowthrough SRAMs, respectively

designed to interface with high-speed microprocessors with

minimum glue logic. Maximum access delay from clock rise is

6.5 ns (133-MHz version). A 2-bit on-chip counter captures the

first address in a burst and increments the address automati-

cally for the rest of the burst access. All synchronous inputs

are gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

)

• 2.5V I/O supply (V_DDQ

)

• Fast clock-to-output times

— 6.5 ns (133-MHz version)

— 7.5 ns (117-MHz version)

— 8.5 ns (100-MHz version)

[2]

(CE₁), depth-expansion Chip Enables (CE₂and CE₃), Burst

Control inputs (ADSC, ADSP, and ADV), Write Enables BW ,

(

• Provide high-performance 2-1-1-1 access rate

and BWE), and Global Write (GW). Asynchronous inputs

include the Output Enable (OE) and the ZZ pin.

• User-selectable burst counter supporting Intel^

Pentium^interleaved or linear burst sequences

The CY7C1381DV25/CY7C1383DV25 allows either inter-

leaved or linear burst sequences, selected by the MODE input

pin. A HIGH selects an interleaved burst sequence, while a

LOW selects a linear burst sequence. Burst accesses can be

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

(ADSP) or the

initiated with the Processor Address Strobe

• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA

cache Controller Address Strobe (ADSC) inputs. Address

advancement is controlled by the Address Advancement

(ADV) input.

and 165-ball fBGA packages

• JTAG boundary scan for BGA and fBGA packages

• “ZZ” Sleep Mode option

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

The CY7C1381DV25/CY7C1383DV25 operates from a +2.5V

core power supply. All outputs also operate with a +2.5 supply.

All

inputs

and

outputs

are

JEDEC-standard

JESD8-5-compatible.

Selection Guide

133 MHz

117 MHz

7.5

100 MHz

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

6.5

210

8.5

175

190

Notes:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE CE are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05547 Rev. **

Revised August 12, 2004

12 3 4 5 6 7...29

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与CY7C1383DV25-100AI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1383DV25-100AXC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383DV25-100AXI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383DV25-100BGC	CYPRESS	获取价格	Cache SRAM, 1MX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
CY7C1383DV25-100BGI	CYPRESS	获取价格	Cache SRAM, 1MX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
CY7C1383DV25-100BGXC	CYPRESS	获取价格	Cache SRAM, 1MX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119
CY7C1383DV25-100BGXI	CYPRESS	获取价格	Cache SRAM, 1MX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119
CY7C1383DV25-100BZC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383DV25-100BZI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383DV25-100BZXC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383DV25-100BZXI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

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