Datasheet > CY7C1383B-133AC

CY7C1383B-133AC

更新时间： 2024-11-14 08:03:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
30页	844K
描述
Standard SRAM, 1MX18, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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CY7C1383B-133AC 数据手册

1CY7C1381B

CY7C1381B

CY7C1383B

PRELIMINARY

512K x 36 / 1 Mb x 18 Flow-Thru SRAM

nal burst operation. All synchronous inputs are gated by reg-

isters controlled by a positive-edge-triggered clock input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining Chip Enable (CE), Burst Control In-

Features

• Fast access times: 6.5, 7.5, 8.5 ns

• Fast clock speed: 133, 117, 100 MHz

• Provide high-performance 3-1-1-1 access rate

• Optimal for depth expansion

puts (ADSC, ADSP, and ADV), Write Enables (BWa, BWb,

BWc, BWd, and BWe), and Global Write (GW).

• 3.3V (–5% / +10%) power supply

Asynchronous inputs include the Output Enable (OE) and

Burst Mode Control (MODE). The data outputs (Q), enabled

by OE, are also asynchronous.

• Common data inputs and data outputs

• Byte Write Enable and Global Write control

• Chip enable for address pipeline

• Address, data and control registers

• Internally self-timed Write Cycle

• Burst control pins (interleaved or linear burst se-

quence)

• Automatic power-down for portable applications

• High-density, high-speed packages

Addresses and chip enables are registered with either Ad-

dress Status Processor (ADSP) or address status controller

(ADSC) input pins. Subsequent burst addresses can be inter-

nally generated as controlled by the Burst Advance Pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate self-timed WRITE cycle. WRITE cycles can be one

to four bytes wide as controlled by the write control inputs.

Individual byte write allows individual byte to be written. BWa

controls DQ1-DQ8 and DQP1. BWb controls DQ9-DQ16 and

DQP2. BWc controls DQ17-DQ24and DQP3. BWd controls

DQ25-DQ32 and DQP4. BWa, BWb BWc, and BWd can be

active only with BWe being LOW. GW being LOW causes all

bytes to be written. WRITE pass-through capability allows writ-

ten data available at the output for the immediately next READ

cycle. This device also incorporates pipelined enable circuit for

easy depth expansion without penalizing system performance.

• JTAG boundary scan for BGA packaging version

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low power CMOS designs using advanced sin-

gle-layer polysilicon, triple-layer metal technology. Each mem-

ory cell consists of six transistors.

The CY7C1381B and CY7C1383A SRAMs integrate

524,288x36 and 1,048,576x18 SRAM cells with advanced

synchronous peripheral circuitry and a 2-bit counter for inter-

All inputs and outputs of the CY7C1381B and the CY7C1383A

are JEDEC standard JESD8-5 compatible.

Selection Guide

-133 MHz

6.5

-117 MHz

7.5

-100 MHz

8.5

Maximum Access Time (ns)

Maximum Operating Current (mA)

200

175

150

Maximum CMOS Standby Current (mA)

Shaded areas contain advance information

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

July 2, 2001

12 3 4 5 6 7...30

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与CY7C1383B-133AC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1383B-133BGC	CYPRESS	获取价格	Standard SRAM, 1MX18, 6.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
CY7C1383B-83AC	CYPRESS	获取价格	512 】 36/1M 】 18 Flow-Thru SRAM
CY7C1383B-83AI	CYPRESS	获取价格	512 】 36/1M 】 18 Flow-Thru SRAM
CY7C1383B-83BGC	CYPRESS	获取价格	512 】 36/1M 】 18 Flow-Thru SRAM
CY7C1383B-83BGI	CYPRESS	获取价格	512 】 36/1M 】 18 Flow-Thru SRAM
CY7C1383B-83BZC	CYPRESS	获取价格	512 】 36/1M 】 18 Flow-Thru SRAM
CY7C1383B-83BZI	CYPRESS	获取价格	512 】 36/1M 】 18 Flow-Thru SRAM
CY7C1383BV25	ETC	获取价格	Memory
CY7C1383BV25-100AC	CYPRESS	获取价格	Standard SRAM, 1MX18, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1383BV25-100AI	CYPRESS	获取价格	Standard SRAM, 1MX18, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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