25
CY7C1380AV25
CY7C1382AV25
PRELIMINARY
512K x 36 / 1M x 18 Pipelined SRAM
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE), burst control in-
puts (ADSC, ADSP, and ADV), Write Enables (BWa, BWb,
BWc, BWd and BWE), and global write (GW).
Features
• Fast clock speed: 167, 150, 133, 100 MHz
• Provide high-performance 3-1-1-1 access rate
• Fast OE access times: 3.4, 3.8, 4.2, 5.0 ns
• Optimal for depth expansion
Asynchronous inputs include the output enable (OE) and burst
mode control (MODE). The data (DQ
) and the data parity
a,b,c,d
(DQP
) outputs, enabled by OE, are also asynchronous.
a,b,c,d
• 2.5V (±5%) Operation
DQ
and DQP
apply to CY7C1380AV25 and DQ
a,b
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Chip enable for address pipeline
a,b,c,d
a,b,c,d
and DQP apply to CY7C1382AV25. a, b, c, d each are of 8
bits wide in the case of DQ and 1 bit wide in the case of DP.
a,b
Addresses and chip enables are registered with either address
status processor (ADSP) or address status controller (ADSC)
input pins. Subsequent burst addresses can be internally gen-
erated as controlled by the burst advance pin (ADV).
• Address, data, and control registers
• Internally self-timed WRITE CYCLE
• Burst control pins (interleaved or linear burst se-
quence)
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQa and DQPa. BWb controls DQb and DQPb. BWc
controls DQc and DQPd. BWd controls DQd-DQd and DQPd.
BWa, BWb BWc, and BWd can be active only with BWE being
LOW. GW being LOW causes all bytes to be written. WRITE
pass-through capability allows written data available at the out-
put for the immediately next READ cycle. This device also in-
corporates pipelined enable circuit for easy depth expansion
without penalizing system performance.
• Automatic power-down for portable applications
• High-density, high-speed packages
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced tri-
ple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high-valued
resistors.
The CY7C1382AV25 and CY7C1380AV25 SRAMs integrate
1,048,576x18 and 524,288x36 SRAM cells with advanced
synchronous peripheral circuitry and a 2-bit counter for inter-
nal burst operation. All synchronous inputs are gated by reg-
isters controlled by a positive-edge-triggered clock input
All inputs and outputs of the CY7C1380AV25 and the
CY7C1382AV25 are JEDEC standard JESD8-5 compatible.
Selection Guide
167 MHz
3.4
150 MHz
3.8
133 MHz
4.2
100 MHz
5.0
Maximum Access Time (ns)
Maximum Operating Current (mA)
Commercial
350
310
280
250
Maximum CMOS Standby Current (mA)
30
30
30
30
Shaded areas contain advance information.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
May 19, 2000
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