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CY7C1367C-225AXC

更新时间： 2024-11-23 23:13:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
27页 457K
描述
9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM

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中文翻译

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CY7C1367C-225AXC 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete包装说明：LQFP, QFP100,.63X.87
Reach Compliance Code：compliant风险等级：5.84
最长访问时间：2.8 ns最大时钟频率 (fCLK)：225 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e3长度：20 mm
内存密度：9437184 bit内存集成电路类型：CACHE DRAM MODULE
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：100
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：512KX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.03 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.25 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

CY7C1367C-225AXC 数据手册

 浏览型号CY7C1367C-225AXC的Datasheet PDF文件第2页浏览型号CY7C1367C-225AXC的Datasheet PDF文件第3页浏览型号CY7C1367C-225AXC的Datasheet PDF文件第4页浏览型号CY7C1367C-225AXC的Datasheet PDF文件第5页浏览型号CY7C1367C-225AXC的Datasheet PDF文件第6页浏览型号CY7C1367C-225AXC的Datasheet PDF文件第7页 
CY7C1366C  
CY7C1367C  
PRELIMINARY  
9-Mbit (256K x 36/512K x 18) Pipelined DCD  
Sync SRAM  
Features  
Functional Description[1]  
• Supports bus operation up to 225 MHz  
The CY7C1366C/CY7C1367C SRAM integrates 262,144 x 36  
and 524,288 x 18 SRAM cells with advanced synchronous  
peripheral circuitry and a two-bit counter for internal burst  
operation. All synchronous inputs are gated by registers  
controlled by a positive-edge-triggered Clock Input (CLK). The  
synchronous inputs include all addresses, all data inputs,  
• Available speed grades are 225, 200 and 166 MHz  
• Registered inputs and outputs for pipelined operation  
•Optimal for performance (Double-Cycle deselect)  
—Depth expansion without wait state  
•3.3V –5% and +10% core power supply (VDD  
• 2.5V / 3.3V I/O operation  
address-pipelining Chip Enable (  
), depth-expansion Chip  
CE1  
)
Enables (CE and  
[2]), Burst Control inputs (  
,
,
CE3  
2
ADSC ADSP  
), Write Enables (  
, and  
BWX  
), and Global Write  
and  
ADV  
BWE  
(
). Asynchronous inputs include the Output Enable (  
GW  
)
OE  
• Fast clock-to-output times  
and the ZZ pin.  
— 2.8 ns (for 225-MHz device)  
— 3.0 ns (for 200-MHz device)  
— 3.5 ns (for 166-MHz device)  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor ( ) or  
ADSP  
) are active. Subsequent  
Address Strobe Controller (  
ADSC  
burst addresses can be internally generated as controlled by  
the Advance pin ( ).  
• Provide high-performance 3-1-1-1 access rate  
ADV  
• User-selectable burst counter supporting Intel  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed Write cycle.This part supports Byte Write  
operations (see Pin Descriptions and Truth Table for further  
details). Write cycles can be one to four bytes wide as  
Pentiuminterleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self-timed writes  
• Asynchronous output enable  
controlled by the byte write control inputs.  
active  
GW  
LOW  
This device incorporates an  
causes all bytes to be written.  
additional pipelined enable register which delays turning off  
the output buffers an additional cycle when a deselect is  
executed.This feature allows depth expansion without penal-  
izing system performance.  
• AvailableinLead-Free100TQFP,119BGAand165fBGA  
packages  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• “ZZ” Sleep Mode Option  
The CY7C1366C/CY7C1367C operates from a +3.3V core  
power supply while all outputs operate with a +3.3V or a +2.5V  
supply. All inputs and outputs are JEDEC-standard  
JESD8-5-compatible.  
Selection Guide  
225 MHz  
200 MHz  
3.0  
166 MHz  
3.5  
Unit  
ns  
mA  
mA  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
2.8  
250  
30  
220  
30  
180  
30  
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.  
Notes:  
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
2. CE is for TQFP and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable.  
3
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05542 Rev. *A  
Revised October 5, 2004  
1234567...27

中文翻译

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