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CY7C1361B-100AJC PDF预览

CY7C1361B-100AJC

更新时间： 2024-11-26 22:19:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
34页 820K
描述
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM

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CY7C1361B-100AJC 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：QFP包装说明：14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
针数：100Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
Factory Lead Time：1 week风险等级：5.75
Is Samacsys：N最长访问时间：8.5 ns
其他特性：FLOW-THROUGH ARCHITECTURE最大时钟频率 (fCLK)：100 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
长度：20 mm内存密度：9437184 bit
内存集成电路类型：CACHE SRAM内存宽度：36
功能数量：1端子数量：100
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：256KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.03 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.18 mA
最大供电电压 (Vsup)：3.63 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD宽度：14 mm
Base Number Matches：1

CY7C1361B-100AJC 数据手册

 浏览型号CY7C1361B-100AJC的Datasheet PDF文件第2页浏览型号CY7C1361B-100AJC的Datasheet PDF文件第3页浏览型号CY7C1361B-100AJC的Datasheet PDF文件第4页浏览型号CY7C1361B-100AJC的Datasheet PDF文件第5页浏览型号CY7C1361B-100AJC的Datasheet PDF文件第6页浏览型号CY7C1361B-100AJC的Datasheet PDF文件第7页 
CY7C1361B  
CY7C1363B  
9-Mbit (256K x 36/512K x 18)  
Flow-Through SRAM  
Features  
Functional Description[1]  
• Supports 133-MHz bus operations  
• 256K X 36/512K X 18 common I/O  
The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K  
x 18 Synchronous Flow through SRAMs, respectively  
designed to interface with high-speed microprocessors with  
minimum glue logic. Maximum access delay from clock rise is  
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the  
first address in a burst and increments the address automati-  
cally for the rest of the burst access. All synchronous inputs  
are gated by registers controlled by a positive-edge-triggered  
Clock Input (CLK). The synchronous inputs include all  
• 3.3V –5% and +10% core power supply (VDD  
)
• 2.5V or 3.3V I/O supply (VDDQ  
• Fast clock-to-output times  
— 6.5 ns (133-MHz version)  
)
— 7.5 ns (117-MHz version)  
— 8.5 ns (100-MHz version)  
addresses, all data inputs, address-pipelining Chip Enable  
[2]  
(
), depth-expansion Chip Enables (CE and  
), Burst  
CE3  
• Provide high-performance 2-1-1-1 access rate  
CE1  
2
Control inputs (  
,
,
), Write Enables  
(
ADV  
BWx  
• User-selectable burst counter supporting Intel  
and  
,
ADSC ADSP  
Pentiuminterleaved or linear burst sequences  
), and Global Write (  
BWE  
). Asynchronous  
GW  
and  
inputs  
(
)
and the ZZ pin  
OE  
.
include the Output Enable  
• Separate processor and controller address strobes  
• Synchronous self-timed write  
The CY7C1361B/CY7C1363B allows either interleaved or  
linear burst sequences, selected by the MODE input pin. A  
HIGH selects an interleaved burst sequence, while a LOW  
selects a linear burst sequence. Burst accesses can be  
initiated with the Processor Address Strobe (ADSP) or the  
cache Controller Address Strobe (ADSC) inputs. Address  
advancement is controlled by the Address Advancement  
(ADV) input.  
• Asynchronous output enable  
• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA  
and 165-ball fBGA packages  
— Both 2 and 3 Chip Enable Options for TQFP  
• JTAG boundary scan for BGA and fBGA packages  
• “ZZ” Sleep Mode option  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (  
) or  
ADSP  
Address Strobe Controller (  
) are active. Subsequent  
ADSC  
burst addresses can be internally generated as controlled by  
the Advance pin ( ).  
ADV  
The CY7C1361B/CY7C1363B operates from a +3.3V core  
power supply while all outputs may operate with either a +2.5  
or +3.3V supply. All inputs and outputs are JEDEC-standard  
JESD8-5-compatible.  
Selection Guide  
133 MHz  
117 MHz  
7.5  
100 MHz  
8.5  
Unit  
ns  
mA  
mA  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
6.5  
250  
30  
220  
30  
180  
30  
Notes:  
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
2. CE is for A version of TQFP (3 Chip Enable Option) and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable.  
3
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05302 Rev. *B  
Revised April 20, 2004  
1234567...34

中文翻译

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