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CY7C1360C-200AJXCT PDF预览

CY7C1360C-200AJXCT

更新时间： 2024-11-24 13:07:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
37页 1179K
描述
QDR SRAM, 256KX36, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100

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CY7C1360C-200AJXCT 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP,针数：100
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.44
Is Samacsys：N最长访问时间：3 ns
其他特性：PIPELINED ARCHITECTUREJESD-30 代码：R-PQFP-G100
JESD-609代码：e3/e4长度：20 mm
内存密度：9437184 bit内存集成电路类型：QDR SRAM
内存宽度：36功能数量：1
端子数量：100字数：262144 words
字数代码：256000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：256KX36封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：MATTE TIN/NICKEL PALLADIUM GOLD端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
宽度：14 mmBase Number Matches：1

CY7C1360C-200AJXCT 数据手册

 浏览型号CY7C1360C-200AJXCT的Datasheet PDF文件第2页浏览型号CY7C1360C-200AJXCT的Datasheet PDF文件第3页浏览型号CY7C1360C-200AJXCT的Datasheet PDF文件第4页浏览型号CY7C1360C-200AJXCT的Datasheet PDF文件第5页浏览型号CY7C1360C-200AJXCT的Datasheet PDF文件第6页浏览型号CY7C1360C-200AJXCT的Datasheet PDF文件第7页 
CY7C1360C, CY7C1362C  
9-Mbit (256 K × 36/512 K × 18)  
Pipelined SRAM  
9-Mbit (256  
K × 36/512 K × 18) Pipelined SRAM  
Features  
Functional Description  
■ Supports bus operation up to 200 MHz  
The CY7C1360C/CY7C1362C SRAM integrates 256 K × 36 and  
512 K × 18 SRAM cells with advanced synchronous peripheral  
circuitry and a two-bit counter for internal burst operation. All  
synchronous inputs are gated by registers controlled by a  
positive-edge-triggered clock input (CLK). The synchronous  
inputs include all addresses, all data inputs, address-pipelining  
chip enable (CE1), depth-expansion chip enables (CE2 and  
■ Available speed grades: 200 MHz, and 166 MHz  
■ Registered inputs and outputs for pipelined operation  
■ 3.3 V core power supply (VDD  
)
■ 2.5 V/3.3 V I/O operation (VDDQ  
)
CE3[1]), burst control inputs (ADSC, ADSP,  
ADV), write  
and  
■ Fast clock-to-output times  
❐ 3.0 ns (for 200 MHz device)  
enables (BWX, and BWE), and global write (GW). Asynchronous  
inputs include the output enable (OE) and the ZZ pin.  
Addresses and chip enables are registered at the rising edge of  
clock when either address strobe processor (ADSP) or address  
strobe controller (ADSC) are active. Subsequent burst  
addresses can be internally generated as controlled by the  
advance pin (ADV).  
■ Provide high performance 3-1-1-1 access rate  
■ User selectable burst counter supporting IntelPentium®  
interleaved or linear burst sequences  
■ Separate processor and controller address strobes  
■ Synchronous self-timed writes  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed write cycle.This part supports byte write  
operations (see Pin Definitions on page 8 and Truth Table on  
page 11 for further details). Write cycles can be one to two or four  
bytes wide as controlled by the byte write control inputs. GW  
■ Asynchronous output enable  
■ Single cycle chip deselect  
when active LOW cause  
s all bytes to be written.  
■ Available in Pb-free 100-pin TQFP package, non Pb-free  
The CY7C1360C/CY7C1362C operate from a +3.3 V core power  
supply while all outputs may operate with either a +2.5 or +3.3 V  
supply. All inputs and outputs are JEDEC-standard  
JESD8-5-compatible.  
119-ball BGA package, and 165-ball FBGA package  
■ TQFP available with 3-chip enable and 2-chip enable  
■ IEEE 1149.1 JTAG-compatible boundary scan  
Selection Guide  
Description  
Maximum access time  
200 MHz  
3.0  
166 MHz Unit  
3.5  
180  
40  
ns  
Maximum operating current  
220  
mA  
mA  
Maximum CMOS standby current  
40  
Note  
1. CE is for A version of TQFP (3 Chip Enable option) and 165-ball FBGA package only. 119-ball BGA is offered only in 2 Chip Enable.  
3
Cypress Semiconductor Corporation  
Document Number: 38-05540 Rev. *N  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised September 25, 2012  
1234567...37

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CY7C1360C-200AJXCT 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1360B-200AJC CYPRESS

完全替代

 9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1360C-200AJXC CYPRESS

类似代替

 9-Mbit (256K x 36/512K x 18) Pipelined SRAM

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