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CY7C1357C-100BGXI PDF预览

CY7C1357C-100BGXI

更新时间： 2024-11-19 03:57:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
28页 499K
描述
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL⑩ Architecture

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CY7C1357C-100BGXI 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119
针数：119Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.76Is Samacsys：N
最长访问时间：7.5 ns其他特性：FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK)：100 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B119JESD-609代码：e1
长度：22 mm内存密度：9437184 bit
内存集成电路类型：ZBT SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：119字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：512KX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA119,7X17,50封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：2.4 mm
最大待机电流：0.04 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.18 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：20宽度：14 mm
Base Number Matches：1

CY7C1357C-100BGXI 数据手册

 浏览型号CY7C1357C-100BGXI的Datasheet PDF文件第2页浏览型号CY7C1357C-100BGXI的Datasheet PDF文件第3页浏览型号CY7C1357C-100BGXI的Datasheet PDF文件第4页浏览型号CY7C1357C-100BGXI的Datasheet PDF文件第5页浏览型号CY7C1357C-100BGXI的Datasheet PDF文件第6页浏览型号CY7C1357C-100BGXI的Datasheet PDF文件第7页 
CY7C1355C  
CY7C1357C  
9-Mbit (256K x 36/512K x 18)  
Flow-Through SRAM with NoBL™ Architecture  
Functional Description[1]  
Features  
• No Bus Latency™ (NoBL™) architecture eliminates  
dead cycles between write and read cycles  
The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18  
Synchronous Flow-through Burst SRAM designed specifically  
to support unlimited true back-to-back Read/Write operations  
• Can support up to 133-MHz bus operations with zero  
wait states  
without  
the  
insertion  
of  
wait  
states.  
The  
CY7C1355C/CY7C1357C is equipped with the advanced No  
Bus Latency (NoBL) logic required to enable consecutive  
Read/Write operations with data being transferred on every  
clock cycle. This feature dramatically improves the throughput  
of data through the SRAM, especially in systems that require  
frequent Write-Read transitions.  
— Data is transferred on every clock  
• Pin compatible and functionally equivalent to ZBT™  
devices  
• Internally self-timed output buffer control to eliminate  
the need to use OE  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. The clock input is qualified by  
the Clock Enable (CEN) signal, which when deasserted  
suspends operation and extends the previous clock cycle.  
Maximum access delay from the clock rise is 6.5 ns (133-MHz  
device).  
• Registered inputs for flow-through operation  
• Byte Write capability  
• 3.3V/2.5V I/O power supply (VDDQ  
)
• Fast clock-to-output times  
— 6.5 ns (for 133-MHz device)  
Write operations are controlled by the two or four Byte Write  
Select (BWX) and a Write Enable (WE) input. All writes are  
conducted with on-chip synchronous self-timed write circuitry.  
• Clock Enable (CEN) pin to enable clock and suspend  
operation  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. In order to avoid bus  
contention, the output drivers are synchronously tri-stated  
during the data portion of a write sequence.  
• Synchronous self-timed writes  
• Asynchronous Output Enable  
• Available in JEDEC-standard and lead-free 100-Pin  
TQFP, lead-free and non lead-free 119-Ball BGA  
package and 165-Ball FBGA package  
• Three chip enables for simple depth expansion.  
• Automatic Power-down feature available using ZZ  
mode or CE deselect  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• Burst Capability—linear or interleaved burst order  
• Low standby power  
Selection Guide  
133 MHz  
6.5  
100 MHz  
7.5  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
250  
180  
mA  
mA  
40  
40  
Note:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05539 Rev. *E  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised September 14, 2006  
[+] Feedback  
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