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CY7C1356CV25-225BGC PDF预览

CY7C1356CV25-225BGC

更新时间： 2024-11-08 09:43:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
25页 338K
描述
9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture

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中文翻译

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CY7C1356CV25-225BGC 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：ObsoleteReach Compliance Code：compliant
风险等级：5.92最长访问时间：2.8 ns
最大时钟频率 (fCLK)：225 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B119JESD-609代码：e0
内存密度：9437184 bit内存集成电路类型：ZBT SRAM
内存宽度：18湿度敏感等级：1
端子数量：119字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：512KX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA119,7X17,50封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：225电源：2.5 V
认证状态：Not Qualified最大待机电流：0.035 A
最小待机电流：2.38 V子类别：SRAMs
最大压摆率：0.25 mA标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED

CY7C1356CV25-225BGC 数据手册

 浏览型号CY7C1356CV25-225BGC的Datasheet PDF文件第2页浏览型号CY7C1356CV25-225BGC的Datasheet PDF文件第3页浏览型号CY7C1356CV25-225BGC的Datasheet PDF文件第4页浏览型号CY7C1356CV25-225BGC的Datasheet PDF文件第5页浏览型号CY7C1356CV25-225BGC的Datasheet PDF文件第6页浏览型号CY7C1356CV25-225BGC的Datasheet PDF文件第7页 
CY7C1354CV25  
CY7C1356CV25  
PRELIMINARY  
9-Mbit (256K x 36/512K x 18) Pipelined SRAM  
with NoBL™ Architecture  
Features  
Functional Description  
• Pin-compatible with and functionally equivalent to  
ZBT™  
The CY7C1354CV25 and CY7C1356CV25 are 2.5V, 256K x  
36 and 512K x 18 Synchronous pipelined burst SRAMs with  
No Bus Latency™ (NoBL™) logic, respectively. They are  
designed to support unlimited true back-to-back Read/Write  
operations with no wait states. The CY7C1354CV25 and  
CY7C1356CV25 are equipped with the advanced (NoBL) logic  
required to enable consecutive Read/Write operations with  
data being transferred on every clock cycle. This feature  
dramatically improves the throughput of data in systems that  
require frequent Write/Read transitions. The CY7C1354CV25  
and CY7C1356CV25 are pin-compatible with and functionally  
equivalent to ZBT devices.  
• Supports 225-MHz bus operations with zero wait states  
— Available speed grades are 225, 200, and 167 MHz  
• Internally self-timed output buffer control to eliminate  
the need to use asynchronous OE  
• Fully registered (inputs and outputs) for pipelined  
operation  
• Byte Write capability  
• Single 2.5V power supply  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock. The  
clock input is qualified by the Clock Enable (CEN) signal,  
which when deasserted suspends operation and extends the  
previous clock cycle.  
• Fast clock-to-output times  
— 2.8 ns (for 225-MHz device)  
— 3.2ns (for 200-MHz device)  
— 3.5 ns (for 167-MHz device)  
• Clock Enable (CEN) pin to suspend operation  
• Synchronous self-timed writes  
Write operations are controlled by the Byte Write Selects  
(BWa–BWd for CY7C1354CV25 and BWa–BWb for  
CY7C1356CV25) and a Write Enable (WE) input. All writes are  
conducted with on-chip synchronous self-timed write circuitry.  
• Available in lead-free 100 TQFP, 119 BGA, and 165 fBGA  
packages  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output three-state control. In order to avoid bus  
contention, the output drivers are synchronously three-stated  
during the data portion of a write sequence.  
• IEEE 1149.1 JTAG Boundary Scan  
• Burst capability–linear or interleaved burst order  
• “ZZ” Sleep Mode option and Stop Clock option  
Logic Block Diagram–CY7C1354CV25 (256K x 36)  
ADDRESS  
REGISTER 0  
A0, A1, A  
A1  
A0  
A1'  
A0'  
D1  
D0  
Q1  
Q0  
BURST  
LOGIC  
MODE  
C
ADV/LD  
C
CLK  
CEN  
WRITE ADDRESS  
REGISTER 1  
WRITE ADDRESS  
REGISTER 2  
O
O
S
U
D
A
T
U
T
P
T
P
E
N
S
U
T
U
T
ADV/LD  
A
E
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
R
E
G
I
MEMORY  
ARRAY  
B
U
F
S
T
E
E
R
I
DQs  
DQP  
DQP  
DQP  
DQP  
WRITE  
DRIVERS  
BW  
BW  
a
a
b
c
d
A
M
P
b
BW  
BW  
c
S
T
E
R
S
F
d
E
R
S
S
WE  
E
E
N
G
INPUT  
REGISTER 1  
INPUT  
REGISTER 0  
E
E
OE  
READ LOGIC  
CE1  
CE2  
CE3  
SLEEP  
CONTROL  
ZZ  
Cypress Semiconductor Corporation  
Document #: 38-05537 Rev. *B  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised November 1, 2004  
1234567...25

中文翻译

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与CY7C1356CV25-225BGC相关器件

型号 品牌 获取价格 描述 数据表
CY7C1356CV25-225BGI CYPRESS

获取价格

 		9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture
CY7C1356CV25-225BGXC CYPRESS

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 		9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture
CY7C1356CV25-225BGXI CYPRESS

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 		9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture
CY7C1356CV25-225BZC CYPRESS

获取价格

 		9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture
CY7C1356CV25-225BZI CYPRESS

获取价格

 		9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture
CY7C1356CV25-225BZXC CYPRESS

获取价格

 		9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture
CY7C1356CV25-225BZXI CYPRESS

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 		9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture
CY7C1356CV25-250AXC ROCHESTER

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 		512KX18 ZBT SRAM, 2.8ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026,
CY7C1356CV25-250AXCT CYPRESS

获取价格

 		ZBT SRAM, 512KX18, 2.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, M
CY7C1356CV25-250BGXC CYPRESS

获取价格

 		ZBT SRAM, 512KX18, 2.8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119

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