5秒后页面跳转
捷配首页

Datasheet > 存储 > SRAM> CY7C1356CV25-167BZXC
CY7C1356CV25-167BZXC PDF预览

CY7C1356CV25-167BZXC

更新时间： 2024-11-08 09:43:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
25页 338K
描述
9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture

阅读下载

中文翻译

获取价格

CY7C1356CV25-167BZXC 数据手册

 浏览型号CY7C1356CV25-167BZXC的Datasheet PDF文件第2页浏览型号CY7C1356CV25-167BZXC的Datasheet PDF文件第3页浏览型号CY7C1356CV25-167BZXC的Datasheet PDF文件第4页浏览型号CY7C1356CV25-167BZXC的Datasheet PDF文件第5页浏览型号CY7C1356CV25-167BZXC的Datasheet PDF文件第6页浏览型号CY7C1356CV25-167BZXC的Datasheet PDF文件第7页 
CY7C1354CV25  
CY7C1356CV25  
PRELIMINARY  
9-Mbit (256K x 36/512K x 18) Pipelined SRAM  
with NoBL™ Architecture  
Features  
Functional Description  
• Pin-compatible with and functionally equivalent to  
ZBT™  
The CY7C1354CV25 and CY7C1356CV25 are 2.5V, 256K x  
36 and 512K x 18 Synchronous pipelined burst SRAMs with  
No Bus Latency™ (NoBL™) logic, respectively. They are  
designed to support unlimited true back-to-back Read/Write  
operations with no wait states. The CY7C1354CV25 and  
CY7C1356CV25 are equipped with the advanced (NoBL) logic  
required to enable consecutive Read/Write operations with  
data being transferred on every clock cycle. This feature  
dramatically improves the throughput of data in systems that  
require frequent Write/Read transitions. The CY7C1354CV25  
and CY7C1356CV25 are pin-compatible with and functionally  
equivalent to ZBT devices.  
• Supports 225-MHz bus operations with zero wait states  
— Available speed grades are 225, 200, and 167 MHz  
• Internally self-timed output buffer control to eliminate  
the need to use asynchronous OE  
• Fully registered (inputs and outputs) for pipelined  
operation  
• Byte Write capability  
• Single 2.5V power supply  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock. The  
clock input is qualified by the Clock Enable (CEN) signal,  
which when deasserted suspends operation and extends the  
previous clock cycle.  
• Fast clock-to-output times  
— 2.8 ns (for 225-MHz device)  
— 3.2ns (for 200-MHz device)  
— 3.5 ns (for 167-MHz device)  
• Clock Enable (CEN) pin to suspend operation  
• Synchronous self-timed writes  
Write operations are controlled by the Byte Write Selects  
(BWa–BWd for CY7C1354CV25 and BWa–BWb for  
CY7C1356CV25) and a Write Enable (WE) input. All writes are  
conducted with on-chip synchronous self-timed write circuitry.  
• Available in lead-free 100 TQFP, 119 BGA, and 165 fBGA  
packages  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output three-state control. In order to avoid bus  
contention, the output drivers are synchronously three-stated  
during the data portion of a write sequence.  
• IEEE 1149.1 JTAG Boundary Scan  
• Burst capability–linear or interleaved burst order  
• “ZZ” Sleep Mode option and Stop Clock option  
Logic Block Diagram–CY7C1354CV25 (256K x 36)  
ADDRESS  
REGISTER 0  
A0, A1, A  
A1  
A0  
A1'  
A0'  
D1  
D0  
Q1  
Q0  
BURST  
LOGIC  
MODE  
C
ADV/LD  
C
CLK  
CEN  
WRITE ADDRESS  
REGISTER 1  
WRITE ADDRESS  
REGISTER 2  
O
O
S
U
D
A
T
U
T
P
T
P
E
N
S
U
T
U
T
ADV/LD  
A
E
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
R
E
G
I
MEMORY  
ARRAY  
B
U
F
S
T
E
E
R
I
DQs  
DQP  
DQP  
DQP  
DQP  
WRITE  
DRIVERS  
BW  
BW  
a
a
b
c
d
A
M
P
b
BW  
BW  
c
S
T
E
R
S
F
d
E
R
S
S
WE  
E
E
N
G
INPUT  
REGISTER 1  
INPUT  
REGISTER 0  
E
E
OE  
READ LOGIC  
CE1  
CE2  
CE3  
SLEEP  
CONTROL  
ZZ  
Cypress Semiconductor Corporation  
Document #: 38-05537 Rev. *B  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised November 1, 2004  
1234567...25

中文翻译

下载PDF

与CY7C1356CV25-167BZXC相关器件

型号 品牌 获取价格 描述 数据表
CY7C1356CV25-167BZXI CYPRESS

获取价格

 		9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture
CY7C1356CV25-200AXC CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1356CV25-200AXI CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1356CV25-200BGC CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1356CV25-200BGI CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1356CV25-200BGXC CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1356CV25-200BGXI CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1356CV25-200BZC CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1356CV25-200BZI CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM w
CY7C1356CV25-200BZXC CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM w

与CY7C1356CV25-167BZXC相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证