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CY7C1356CV25-166AXCT

更新时间： 2024-09-19 13:02:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
33页 835K
描述
ZBT SRAM, 512KX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100

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CY7C1356CV25-166AXCT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete包装说明：LQFP, QFP100,.63X.87
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.81
最长访问时间：3.5 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：166 MHzI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e3
长度：20 mm内存密度：9437184 bit
内存集成电路类型：ZBT SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：100字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：512KX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：2.5 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.04 A最小待机电流：2.38 V
子类别：SRAMs最大压摆率：0.18 mA
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：20宽度：14 mm
Base Number Matches：1

CY7C1356CV25-166AXCT 数据手册

 浏览型号CY7C1356CV25-166AXCT的Datasheet PDF文件第2页浏览型号CY7C1356CV25-166AXCT的Datasheet PDF文件第3页浏览型号CY7C1356CV25-166AXCT的Datasheet PDF文件第4页浏览型号CY7C1356CV25-166AXCT的Datasheet PDF文件第5页浏览型号CY7C1356CV25-166AXCT的Datasheet PDF文件第6页浏览型号CY7C1356CV25-166AXCT的Datasheet PDF文件第7页 
CY7C1354CV25  
CY7C1356CV25  
9-Mbit (256 K × 36/512 K × 18)  
Pipelined SRAM with NoBL™ Architecture  
9-Mbit (256  
K × 36/512 K × 18) Pipelined SRAM with NoBL™ Architecture  
Features  
Functional Description  
■ Pin-compatible with and functionally equivalent to ZBT™  
■ Supports 250-MHz bus operations with zero wait states  
■ Available speed grades are 250, 200, and 166 MHz  
The  
CY7C1354CV25/CY7C1356CV25[1]  
are  
2.5 V,  
256 K × 36/512 K × 18 synchronous pipelined burst SRAMs with  
No Bus Latency™ (NoBL logic, respectively. They are  
designed to support unlimited true back-to-back read/write  
operations  
with  
no  
wait  
states.  
The  
■ Internally self-timed output buffer control to eliminate the need  
to use asynchronous OE  
CY7C1354CV25/CY7C1356CV25 are equipped with the  
advanced (NoBL) logic required to enable consecutive  
read/write operations with data being transferred on every clock  
cycle. This feature dramatically improves the throughput of data  
in systems that require frequent write/read transitions. The  
CY7C1354CV25/CY7C1356CV25 are pin-compatible with and  
functionally equivalent to ZBT devices.  
■ Fully registered (inputs and outputs) for pipelined operation  
■ Byte write capability  
■ Single 2.5 V power supply (VDD  
)
■ Fast clock-to-output times  
❐ 2.8 ns (for 250-MHz device)  
All synchronous inputs pass through input registers controlled by  
the rising edge of the clock. All data outputs pass through output  
registers controlled by the rising edge of the clock. The clock  
input is qualified by the clock enable (CEN) signal, which when  
deasserted suspends operation and extends the previous clock  
cycle.  
■ Clock enable (CEN) pin to suspend operation  
■ Synchronous self-timed writes  
■ Available in Pb-free 100-pin TQFP package, Pb-free and  
non Pb-free 119-ball BGA package and 165-ball FBGA  
package  
Write operations are controlled by the byte write selects  
(BWa–BWd for CY7C1354CV25 and BWa–BWb for  
CY7C1356CV25) and a write enable (WE) input. All writes are  
conducted with on-chip synchronous self-timed write circuitry.  
■ IEEE 1149.1 JTAG-compatible boundary scan  
■ Burst capability–linear or interleaved burst order  
■ “ZZ” sleep mode option and stop clock option  
Three synchronous chip enables (CE1, CE2, CE3) and an  
asynchronous output enable (OE) provide for easy bank  
selection and output tri-state control. In order to avoid bus  
contention, the output drivers are synchronously tri-stated during  
the data portion of a write sequence.  
Logic Block Diagram – CY7C1354CV25  
ADDRESS  
REGISTER 0  
A0, A1, A  
A1  
A0  
A1'  
A0'  
D1  
D0  
Q1  
Q0  
BURST  
LOGIC  
MODE  
C
ADV/LD  
C
CLK  
CEN  
WRITE ADDRESS  
REGISTER 1  
WRITE ADDRESS  
REGISTER 2  
O
O
S
U
D
A
T
U
T
P
T
P
E
N
S
U
T
U
T
ADV/LD  
A
E
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
R
E
G
I
MEMORY  
ARRAY  
B
U
F
S
T
E
E
R
I
DQs  
DQP  
DQP  
DQP  
DQP  
WRITE  
DRIVERS  
BW  
BW  
a
a
b
c
d
A
M
P
b
BW  
BW  
c
S
T
E
R
S
F
d
E
R
S
S
WE  
E
E
N
G
INPUT  
REGISTER 1  
INPUT  
REGISTER 0  
E
E
OE  
READ LOGIC  
CE1  
CE2  
CE3  
SLEEP  
CONTROL  
ZZ  
Note  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document Number: 38-05537 Rev. *M  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised September 25, 2012  
1234567...33

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CY7C1356CV25-166AXCT 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1356CV25-166AXC CYPRESS

完全替代

 9-Mbit (256K x 36/512K x 18) Pipelined SRAM w

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