5秒后页面跳转
捷配首页

Datasheet > 存储 > SRAM> CY7C1354DV25-200AXI
CY7C1354DV25-200AXI PDF预览

CY7C1354DV25-200AXI

更新时间： 2024-11-18 06:51:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
29页 847K
描述
9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture

阅读下载

中文翻译

获取价格

CY7C1354DV25-200AXI 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP, QFP100,.63X.87针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.8
最长访问时间：3.2 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：200 MHzI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e3
长度：20 mm内存密度：9437184 bit
内存集成电路类型：ZBT SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端子数量：100字数：262144 words
字数代码：256000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：256KX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：2.5 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.04 A最小待机电流：2.38 V
子类别：SRAMs最大压摆率：0.22 mA
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：20宽度：14 mm
Base Number Matches：1

CY7C1354DV25-200AXI 数据手册

 浏览型号CY7C1354DV25-200AXI的Datasheet PDF文件第2页浏览型号CY7C1354DV25-200AXI的Datasheet PDF文件第3页浏览型号CY7C1354DV25-200AXI的Datasheet PDF文件第4页浏览型号CY7C1354DV25-200AXI的Datasheet PDF文件第5页浏览型号CY7C1354DV25-200AXI的Datasheet PDF文件第6页浏览型号CY7C1354DV25-200AXI的Datasheet PDF文件第7页 
CY7C1354DV25, CY7C1356DV25  
9-Mbit (256K x 36/512K x 18)  
Pipelined SRAM with NoBL™ Architecture  
Features  
Functional Description  
The CY7C1354DV25 and CY7C1356DV25 are 2.5V, 256K x 36  
and 512K x 18 Synchronous pipelined burst SRAMs with No Bus  
Latency™ (NoBL™) logic, respectively. They are designed to  
support unlimited true back to back read and write operations  
with no wait states. The CY7C1354DV25 and CY7C1356DV25  
are equipped with the advanced (NoBL) logic required to enable  
consecutive read and write operations with data being trans-  
ferred on every clock cycle. This feature dramatically improves  
the throughput of data in systems that require frequent write and  
read transitions. The CY7C1354DV25 and CY7C1356DV25 are  
pin compatible with and functionally equivalent to ZBT devices.  
■
■
■
■
Pin compatible with and functionally equivalent to ZBT™  
Supports 250 MHz bus operations with zero wait states  
Available speed grades are 250, 200, and 166 MHz  
Internally self timed output buffer control to eliminate the need  
to use asynchronous OE  
■
■
■
■
Fully registered (inputs and outputs) for pipelined operation  
Byte Write capability  
Single 2.5V power supply (VDD  
Fast clock-to-output times  
)
All synchronous inputs pass through input registers controlled by  
the rising edge of the clock. All data outputs pass through output  
registers controlled by the rising edge of the clock. The clock  
input is qualified by the Clock Enable (CEN) signal, which when  
deasserted suspends operation and extends the previous clock  
cycle.  
❐
2.8 ns (for 250 MHz device)  
■
■
■
Clock Enable (CEN) pin to suspend operation  
Synchronous self timed writes  
Write operations are controlled by the Byte Write Selects  
(BWa–BWd for CY7C1354DV25 and BWa–BWb for  
CY7C1356DV25) and a Write Enable (WE) input. All writes are  
conducted with on-chip synchronous self timed write circuitry.  
Available in Pb-free 100-pin TQFP package, Pb-free and non  
Pb-free 119-ball BGA package, and 165-ball FBGA package  
■
■
■
IEEE 1149.1 JTAG compatible boundary scan  
Burst capability–linear or interleaved burst order  
“ZZ” Sleep mode and Stop Clock options  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide easy bank selection  
and output tri-state control. To avoid bus contention, the output  
drivers are synchronously tri-stated during the data portion of a  
write sequence. For best practices recommendations, please  
refer to the Cypress application note System Design Guidelines  
on www.cypress.com.  
Selection Guide  
Description  
250 MHz  
2.8  
200 MHz  
3.2  
166 MHz  
3.5  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
250  
220  
180  
mA  
mA  
Maximum CMOS Standby Current  
40  
40  
40  
Cypress Semiconductor Corporation  
Document #: 001-48974 Rev. *A  
•
198 Champion Court  
•
San Jose  
,
CA 95134-1709  
•
408-943-2600  
Revised July 31, 2009  
[+] Feedback  
1234567...29

中文翻译

下载PDF

与CY7C1354DV25-200AXI相关器件

型号 品牌 获取价格 描述 数据表
CY7C1354DV25-200BGC CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture
CY7C1354DV25-200BGI CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture
CY7C1354DV25-200BGXC CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture
CY7C1354DV25-200BGXI CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture
CY7C1354DV25-200BZC CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture
CY7C1354DV25-200BZI CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture
CY7C1354DV25-200BZXC CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture
CY7C1354DV25-200BZXI CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture
CY7C1354DV25-250AXC CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture
CY7C1354DV25-250AXI CYPRESS

获取价格

 		9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture

与CY7C1354DV25-200AXI相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证