Datasheet > CY7C1351G_12

CY7C1351G_12

更新时间： 2024-11-26 12:22:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
20页	550K
描述
4-Mbit (128 K Ã 36) Flow-Through SRAM with NoBLâ¢ Architecture

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CY7C1351G_12 数据手册

CY7C1351G

4-Mbit (128 K × 36) Flow-Through SRAM

with NoBL™ Architecture

4-Mbit (128

K × 36) Flow-Through SRAM with NoBL™ Architecture

Features

Functional Description

■ Can support up to 133-MHz bus operations with zero wait

states

❐ Data is transferred on every clock

The CY7C1351G is a 3.3 V, 128 K × 36 synchronous

flow-through burst SRAM designed specifically to support

unlimited true back-to-back read/write operations without the

insertion of wait states. The CY7C1351G is equipped with the

advanced No Bus Latency™ (NoBL™) logic required to enable

consecutive Read/Write operations with data being transferred

on every clock cycle. This feature dramatically improves the

throughput of data through the SRAM, especially in systems that

require frequent write-read transitions.

■ Pin compatible and functionally equivalent to ZBT™ devices

■ Internally self-timed output buffer control to eliminate the need

to use OE

■ Registered inputs for flow-through operation

■ Byte write capability

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. The clock input is qualified by the

clock enable (CEN) signal, which when deasserted suspends

operation and extends the previous clock cycle. Maximum

access delay from the clock rise is 6.5 ns (133-MHz device).

■ 128 K × 36 common I/O architecture

■ 2.5 V/3.3 V I/O power supply (V_DDQ

)

■ Fast clock-to-output times

❐ 6.5 ns (for 133-MHz device)

Write operations are controlled by the four byte write select

(BW_[A:D]) and a write enable (WE) input. All writes are conducted

with on-chip synchronous self-timed write circuitry.

■ Clock enable (CEN) pin to suspend operation

■ Synchronous self-timed writes

Three synchronous chip enables (CE₁, CE₂, CE₃) and an

asynchronous output enable (OE) provide for easy bank

selection and output tristate control. In order to avoid bus

contention, the output drivers are synchronously tristated during

the data portion of a write sequence.

■ Asynchronous output enable

■ Available in Pb-free 100-pin TQFP package

■ Burst capability – linear or interleaved burst order

■ Low standby power

Selection Guide

Description

133 MHz

6.5

100 MHz Unit

Maximum access time

8.0

205

Maximum operating current

Maximum CMOS standby current

225

Cypress Semiconductor Corporation

Document Number: 38-05513 Rev. *K

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised October 5, 2012

12 3 4 5 6 7...20

中文翻译

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与CY7C1351G_12相关器件

型号	品牌	获取价格	描述	数据表
CY7C1351G_13	CYPRESS	获取价格	4-Mbit (128 K x 36) Flow-Through SRAM with No
CY7C1351G-100AXC	CYPRESS	获取价格	4-Mbit (128K x 36) Flow-through SRAM with NoB
CY7C1351G-100AXCT	CYPRESS	获取价格	ZBT SRAM, 128KX36, 8ns, CMOS, PQFP100, 20 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP
CY7C1351G-100AXI	CYPRESS	获取价格	4-Mbit (128K x 36) Flow-through SRAM with NoB
CY7C1351G-100AXIT	CYPRESS	获取价格	ZBT SRAM, 128KX36, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP
CY7C1351G-100BGC	CYPRESS	获取价格	4-Mbit (128K x 36) Flow-through SRAM with NoB
CY7C1351G-100BGCT	CYPRESS	获取价格	ZBT SRAM, 128KX36, 8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
CY7C1351G-100BGI	CYPRESS	获取价格	4-Mbit (128K x 36) Flow-through SRAM with NoB
CY7C1351G-100BGXC	CYPRESS	获取价格	4-Mbit (128K x 36) Flow-through SRAM with NoB
CY7C1351G-100BGXI	CYPRESS	获取价格	4-Mbit (128K x 36) Flow-through SRAM with NoB

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