Datasheet > CY7C1351G

CY7C1351G

更新时间： 2024-11-26 05:19:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
14页	395K
描述
4-Mbit (128K x 36) Flow-through SRAM with NoBL⑩ Architecture

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CY7C1351G 数据手册

CY7C1351G

4-Mbit (128K x 36) Flow-through SRAM

with NoBL™ Architecture

Functional Description^[1]

Features

• Can support up to 133-MHz bus operations with zero

wait states

The CY7C1351G is a 3.3V, 128K x 36 Synchronous

Flow-through Burst SRAM designed specifically to support

unlimited true back-to-back Read/Write operations without the

insertion of wait states. The CY7C1351G is equipped with the

advanced No Bus Latency™ (NoBL™) logic required to

enable consecutive Read/Write operations with data being

transferred on every clock cycle. This feature dramatically

improves the throughput of data through the SRAM, especially

in systems that require frequent Write-Read transitions.

— Data is transferred on every clock

• Pin compatible and functionally equivalent to ZBT™

devices

• Internally self-timed output buffer control to eliminate

the need to use OE

• Registered inputs for flow-through operation

• Byte Write capability

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. The clock input is qualified by

the Clock Enable (CEN) signal, which when deasserted

suspends operation and extends the previous clock cycle.

Maximum access delay from the clock rise is 6.5 ns (133-MHz

device).

• 128K x 36 common I/O architecture

• 2.5V/3.3V I/O power supply (V_DDQ

)

• Fast clock-to-output times

— 6.5 ns (for 133-MHz device)

Write operations are controlled by the four Byte Write Select

(BW_[A:D]) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

• Asynchronous Output Enable

• Available in lead-free 100-Pin TQFP package, lead-free

and non-lead-free 119-Ball BGA package

• Burst Capability—linear or interleaved burst order

• Low standby power

Logic Block Diagram

ADDRESS

A0, A1, A

A1'

A0'

MODE

BURST

LOGIC

ADV/LD

CLK

CEN

WRITE ADDRESS

ADV/LD

MEMORY

ARRAY

BWA

BWB

BWC

BWD

WRITE

DRIVERS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

DQs

DQP

INPUT

READ LOGIC

CE1

CE2

CE3

SLEEP

Control

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05513 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 4, 2006

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与CY7C1351G相关器件

型号	品牌	获取价格	描述	数据表
CY7C1351G_12	CYPRESS	获取价格	4-Mbit (128 K Ã 36) Flow-Through SRAM with N
CY7C1351G_13	CYPRESS	获取价格	4-Mbit (128 K x 36) Flow-Through SRAM with No
CY7C1351G-100AXC	CYPRESS	获取价格	4-Mbit (128K x 36) Flow-through SRAM with NoB
CY7C1351G-100AXCT	CYPRESS	获取价格	ZBT SRAM, 128KX36, 8ns, CMOS, PQFP100, 20 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP
CY7C1351G-100AXI	CYPRESS	获取价格	4-Mbit (128K x 36) Flow-through SRAM with NoB
CY7C1351G-100AXIT	CYPRESS	获取价格	ZBT SRAM, 128KX36, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP
CY7C1351G-100BGC	CYPRESS	获取价格	4-Mbit (128K x 36) Flow-through SRAM with NoB
CY7C1351G-100BGCT	CYPRESS	获取价格	ZBT SRAM, 128KX36, 8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
CY7C1351G-100BGI	CYPRESS	获取价格	4-Mbit (128K x 36) Flow-through SRAM with NoB
CY7C1351G-100BGXC	CYPRESS	获取价格	4-Mbit (128K x 36) Flow-through SRAM with NoB

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