5秒后页面跳转
捷配首页

Datasheet > 存储 > SRAM> CY7C1351G-133BGCT
CY7C1351G-133BGCT PDF预览

CY7C1351G-133BGCT

更新时间： 2024-11-26 13:07:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
14页 395K
描述
ZBT SRAM, 128KX36, 6.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119

阅读下载

中文翻译

获取价格

CY7C1351G-133BGCT 技术参数

生命周期：Obsolete零件包装代码：BGA
包装说明：BGA,针数：119
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.77
最长访问时间：6.5 ns其他特性：FLOW THROUGH ARCHITECTURE
JESD-30 代码：R-PBGA-B119JESD-609代码：e0
长度：22 mm内存密度：4718592 bit
内存集成电路类型：ZBT SRAM内存宽度：36
功能数量：1端子数量：119
字数：131072 words字数代码：128000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：128KX36
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL认证状态：Not Qualified
座面最大高度：2.4 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：TIN LEAD
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM宽度：14 mm
Base Number Matches：1

CY7C1351G-133BGCT 数据手册

 浏览型号CY7C1351G-133BGCT的Datasheet PDF文件第2页浏览型号CY7C1351G-133BGCT的Datasheet PDF文件第3页浏览型号CY7C1351G-133BGCT的Datasheet PDF文件第4页浏览型号CY7C1351G-133BGCT的Datasheet PDF文件第5页浏览型号CY7C1351G-133BGCT的Datasheet PDF文件第6页浏览型号CY7C1351G-133BGCT的Datasheet PDF文件第7页 
CY7C1351G  
4-Mbit (128K x 36) Flow-through SRAM  
with NoBL™ Architecture  
Functional Description[1]  
Features  
• Can support up to 133-MHz bus operations with zero  
wait states  
The CY7C1351G is a 3.3V, 128K x 36 Synchronous  
Flow-through Burst SRAM designed specifically to support  
unlimited true back-to-back Read/Write operations without the  
insertion of wait states. The CY7C1351G is equipped with the  
advanced No Bus Latency™ (NoBL™) logic required to  
enable consecutive Read/Write operations with data being  
transferred on every clock cycle. This feature dramatically  
improves the throughput of data through the SRAM, especially  
in systems that require frequent Write-Read transitions.  
— Data is transferred on every clock  
• Pin compatible and functionally equivalent to ZBT™  
devices  
• Internally self-timed output buffer control to eliminate  
the need to use OE  
• Registered inputs for flow-through operation  
• Byte Write capability  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. The clock input is qualified by  
the Clock Enable (CEN) signal, which when deasserted  
suspends operation and extends the previous clock cycle.  
Maximum access delay from the clock rise is 6.5 ns (133-MHz  
device).  
• 128K x 36 common I/O architecture  
• 2.5V/3.3V I/O power supply (VDDQ  
)
• Fast clock-to-output times  
— 6.5 ns (for 133-MHz device)  
Write operations are controlled by the four Byte Write Select  
(BW[A:D]) and a Write Enable (WE) input. All writes are  
conducted with on-chip synchronous self-timed write circuitry.  
• Clock Enable (CEN) pin to suspend operation  
• Synchronous self-timed writes  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. In order to avoid bus  
contention, the output drivers are synchronously tri-stated  
during the data portion of a write sequence.  
• Asynchronous Output Enable  
• Available in lead-free 100-Pin TQFP package, lead-free  
and non-lead-free 119-Ball BGA package  
• Burst Capability—linear or interleaved burst order  
• Low standby power  
Logic Block Diagram  
ADDRESS  
A0, A1, A  
REGISTER  
A1  
A1'  
A0'  
D1  
A0  
Q1  
Q0  
D0  
MODE  
BURST  
LOGIC  
CE  
ADV/LD  
C
CLK  
CEN  
C
WRITE ADDRESS  
REGISTER  
O
U
T
P
U
T
D
A
T
S
E
N
S
ADV/LD  
A
B
U
F
MEMORY  
ARRAY  
BWA  
BWB  
BWC  
BWD  
WRITE  
DRIVERS  
E
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
S
T
E
E
R
I
DQs  
DQP  
DQP  
DQP  
DQP  
A
B
C
D
A
M
P
F
E
R
S
S
WE  
E
N
G
INPUT  
REGISTER  
E
OE  
READ LOGIC  
CE1  
CE2  
CE3  
SLEEP  
Control  
ZZ  
Note:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05513 Rev. *D  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised July 4, 2006  
[+] Feedback  
1234567...14

中文翻译

下载PDF

与CY7C1351G-133BGCT相关器件

型号 品牌 获取价格 描述 数据表
CY7C1351G-133BGI CYPRESS

获取价格

 		4-Mbit (128K x 36) Flow-through SRAM with NoB
CY7C1351G-133BGXC CYPRESS

获取价格

 		4-Mbit (128K x 36) Flow-through SRAM with NoB
CY7C1351G-133BGXI CYPRESS

获取价格

 		4-Mbit (128K x 36) Flow-through SRAM with NoB
CY7C1352 CYPRESS

获取价格

 		256K x18 Pipelined SRAM with NoBL Architecture
CY7C135-20JC CYPRESS

获取价格

 		4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores
CY7C135-20JCT CYPRESS

获取价格

 		Dual-Port SRAM, 4KX8, 20ns, CMOS, PQCC52, PLASTIC, LCC-52
CY7C1352-100AC CYPRESS

获取价格

 		256K x18 Pipelined SRAM with NoBL Architecture
CY7C1352-100AI ETC

获取价格

 		x18 Fast Synchronous SRAM
CY7C1352-133AC CYPRESS

获取价格

 		256K x18 Pipelined SRAM with NoBL Architecture
CY7C1352-133AI ETC

获取价格

 		x18 Fast Synchronous SRAM

与CY7C1351G-133BGCT相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证