Datasheet > 存储 > SRAM> CY7C1351G-100AXIT

CY7C1351G-100AXIT

更新时间： 2024-11-26 13:07:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
21页	567K
描述
ZBT SRAM, 128KX36, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100

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CY7C1351G-100AXIT 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP,	针数：	100
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.64
Is Samacsys：	N	最长访问时间：	8 ns
其他特性：	FLOW THROUGH ARCHITECTURE	JESD-30 代码：	R-PQFP-G100
JESD-609代码：	e3/e4	长度：	20 mm
内存密度：	4718592 bit	内存集成电路类型：	ZBT SRAM
内存宽度：	36	功能数量：	1
端子数量：	100	字数：	131072 words
字数代码：	128000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	128KX36	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	MATTE TIN/NICKEL PALLADIUM GOLD	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
宽度：	14 mm	Base Number Matches：	1

CY7C1351G-100AXIT 数据手册

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CY7C1351G

4-Mbit (128 K × 36) Flow-Through SRAM

with NoBL™ Architecture

4-Mbit (128

K × 36) Flow-Through SRAM with NoBL™ Architecture

Features

Functional Description

■ Can support up to 133-MHz bus operations with zero wait

states

❐ Data is transferred on every clock

The CY7C1351G is a 3.3 V, 128 K × 36 synchronous

flow-through burst SRAM designed specifically to support

unlimited true back-to-back read/write operations without the

insertion of wait states. The CY7C1351G is equipped with the

advanced No Bus Latency™ (NoBL™) logic required to enable

consecutive Read/Write operations with data being transferred

on every clock cycle. This feature dramatically improves the

throughput of data through the SRAM, especially in systems that

require frequent write-read transitions.

■ Pin compatible and functionally equivalent to ZBT™ devices

■ Internally self-timed output buffer control to eliminate the need

to use OE

■ Registered inputs for flow-through operation

■ Byte write capability

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. The clock input is qualified by the

clock enable (CEN) signal, which when deasserted suspends

operation and extends the previous clock cycle. Maximum

access delay from the clock rise is 6.5 ns (133-MHz device).

■ 128 K × 36 common I/O architecture

■ 2.5 V/3.3 V I/O power supply (V_DDQ

)

■ Fast clock-to-output times

❐ 6.5 ns (for 133-MHz device)

Write operations are controlled by the four byte write select

(BW_[A:D]) and a write enable (WE) input. All writes are conducted

with on-chip synchronous self-timed write circuitry.

■ Clock enable (CEN) pin to suspend operation

■ Synchronous self-timed writes

Three synchronous chip enables (CE₁, CE₂, CE₃) and an

asynchronous output enable (OE) provide for easy bank

selection and output tristate control. In order to avoid bus

contention, the output drivers are synchronously tristated during

the data portion of a write sequence.

■ Asynchronous output enable

■ Available in Pb-free 100-pin TQFP package

■ Burst capability – linear or interleaved burst order

■ Low standby power

Selection Guide

Description

133 MHz

6.5

100 MHz Unit

Maximum access time

8.0

205

Maximum operating current

Maximum CMOS standby current

225

Errata: For information on silicon errata, see "Errata" on page 18. Details include trigger conditions, devices affected, and proposed workaround.

Cypress Semiconductor Corporation

Document Number: 38-05513 Rev. *M

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 25, 2013

12 3 4 5 6 7...21

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与CY7C1351G-100AXIT相关器件

型号	品牌	获取价格	描述	数据表
CY7C1351G-100BGC	CYPRESS	获取价格	4-Mbit (128K x 36) Flow-through SRAM with NoB
CY7C1351G-100BGCT	CYPRESS	获取价格	ZBT SRAM, 128KX36, 8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
CY7C1351G-100BGI	CYPRESS	获取价格	4-Mbit (128K x 36) Flow-through SRAM with NoB
CY7C1351G-100BGXC	CYPRESS	获取价格	4-Mbit (128K x 36) Flow-through SRAM with NoB
CY7C1351G-100BGXI	CYPRESS	获取价格	4-Mbit (128K x 36) Flow-through SRAM with NoB
CY7C1351G-117AXI	CYPRESS	获取价格	ZBT SRAM, 128KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, M
CY7C1351G-117BGC	CYPRESS	获取价格	ZBT SRAM, 128KX36, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1351G-117BGI	CYPRESS	获取价格	ZBT SRAM, 128KX36, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1351G-133AXC	CYPRESS	获取价格	4-Mbit (128K x 36) Flow-through SRAM with NoB
CY7C1351G-133AXI	CYPRESS	获取价格	4-Mbit (128K x 36) Flow-through SRAM with NoB

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