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CY7C1351G-100AXCT PDF预览

CY7C1351G-100AXCT

更新时间： 2024-11-26 19:48:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟静态存储器内存集成电路
页数 文件大小 规格书
23页 393K
描述
ZBT SRAM, 128KX36, 8ns, CMOS, PQFP100, 20 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100

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CY7C1351G-100AXCT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：LQFP, QFP100,.63X.87
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.54
最长访问时间：8 ns其他特性：FLOW THROUGH ARCHITECTURE
最大时钟频率 (fCLK)：100 MHzI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e4
长度：20 mm内存密度：4718592 bit
内存集成电路类型：ZBT SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端子数量：100字数：131072 words
字数代码：128000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：128KX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.04 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.205 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：20宽度：14 mm
Base Number Matches：1

CY7C1351G-100AXCT 数据手册

 浏览型号CY7C1351G-100AXCT的Datasheet PDF文件第2页浏览型号CY7C1351G-100AXCT的Datasheet PDF文件第3页浏览型号CY7C1351G-100AXCT的Datasheet PDF文件第4页浏览型号CY7C1351G-100AXCT的Datasheet PDF文件第5页浏览型号CY7C1351G-100AXCT的Datasheet PDF文件第6页浏览型号CY7C1351G-100AXCT的Datasheet PDF文件第7页 
CY7C1351G  
4-Mbit (128K × 36) Flow-Through SRAM  
with NoBL™ Architecture  
4-Mbit (128K  
× 36) Flow-Through SRAM with NoBL™ Architecture  
Features  
Functional Description  
■ Can support up to 133 MHz bus operations with zero wait states  
❐ Data is transferred on every clock  
The CY7C1351G is a 3.3 V, 128K × 36 synchronous flow-through  
burst SRAM designed specifically to support unlimited true  
back-to-back read/write operations without the insertion of wait  
states. The CY7C1351G is equipped with the advanced No Bus  
Latency™ (NoBL™) logic required to enable consecutive  
Read/Write operations with data being transferred on every clock  
cycle. This feature dramatically improves the throughput of data  
through the SRAM, especially in systems that require frequent  
write-read transitions.  
■ Pin compatible and functionally equivalent to ZBT™ devices  
■ Internally self-timed output buffer control to eliminate the need  
to use OE  
■ Registered inputs for flow-through operation  
■ Byte write capability  
All synchronous inputs pass through input registers controlled by  
the rising edge of the clock. The clock input is qualified by the  
clock enable (CEN) signal, which when deasserted suspends  
operation and extends the previous clock cycle. Maximum  
access delay from the clock rise is 6.5 ns (133-MHz device).  
■ 128K × 36 common I/O architecture  
■ 2.5 V/3.3 V I/O power supply (VDDQ  
)
■ Fast clock-to-output times  
❐ 6.5 ns (for 133 MHz device)  
Write operations are controlled by the four byte write select  
(BW[A:D]) and a write enable (WE) input. All writes are conducted  
with on-chip synchronous self-timed write circuitry.  
■ Clock enable (CEN) pin to suspend operation  
■ Synchronous self-timed writes  
Three synchronous chip enables (CE1, CE2, CE3) and an  
asynchronous output enable (OE) provide for easy bank  
selection and output tristate control. In order to avoid bus  
contention, the output drivers are synchronously tristated during  
the data portion of a write sequence.  
■ Asynchronous output enable  
■ Available in Pb-free 100-pin TQFP package  
■ Burst capability – linear or interleaved burst order  
■ Low standby power  
For a complete list of related documentation, click here.  
Selection Guide  
Description  
133 MHz  
6.5  
100 MHz Unit  
Maximum access time  
8.0  
205  
40  
ns  
Maximum operating current  
Maximum CMOS standby current  
225  
mA  
mA  
40  
Errata: For information on silicon errata, see "Errata" on page 19. Details include trigger conditions, devices affected, and proposed workaround.  
Cypress Semiconductor Corporation  
Document Number: 38-05513 Rev. *R  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised January 9, 2018  
 
 
 
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CY7C1351G-100AXCT 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1351G-100AXC CYPRESS

类似代替

 4-Mbit (128K x 36) Flow-through SRAM with NoB

与CY7C1351G-100AXCT相关器件

型号 品牌 获取价格 描述 数据表
CY7C1351G-100AXI CYPRESS

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 		4-Mbit (128K x 36) Flow-through SRAM with NoB
CY7C1351G-100AXIT CYPRESS

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 		ZBT SRAM, 128KX36, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP
CY7C1351G-100BGC CYPRESS

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 		4-Mbit (128K x 36) Flow-through SRAM with NoB
CY7C1351G-100BGCT CYPRESS

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 		ZBT SRAM, 128KX36, 8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
CY7C1351G-100BGI CYPRESS

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 		4-Mbit (128K x 36) Flow-through SRAM with NoB
CY7C1351G-100BGXC CYPRESS

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 		4-Mbit (128K x 36) Flow-through SRAM with NoB
CY7C1351G-100BGXI CYPRESS

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 		4-Mbit (128K x 36) Flow-through SRAM with NoB
CY7C1351G-117AXI CYPRESS

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 		ZBT SRAM, 128KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, M
CY7C1351G-117BGC CYPRESS

获取价格

 		ZBT SRAM, 128KX36, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1351G-117BGI CYPRESS

获取价格

 		ZBT SRAM, 128KX36, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119

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