Datasheet > CY7C1351B

CY7C1351B

更新时间： 2024-11-25 23:45:27

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
16页	272K
描述
Memory

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中文翻译

获取价格

数据手册

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CY7C1351B 数据手册

351B

PRELIMINARY

CY7C1351B

128Kx36 Flow-Through SRAM with NoBL™ Architecture

Features

Functional Description

• Pincompatible andfunctionallyequivalenttoZBT™ de-

The CY7C1351B is a 3.3V, 128K by 36 Synchronous

Flow-Through Burst SRAM designed specifically to support

unlimited true back-to-back Read/Write operations without the

insertion of wait states. The CY7C1351B is equipped with the

advanced No Bus Latency™ (NoBL™) logic required to en-

able consecutive Read/Write operations with data being trans-

ferred on every clock cycle. This feature dramatically improves

the throughput of data through the SRAM, especially in sys-

tems that require frequent Write/Read transitions. The

CY7C1351B is pin/functionally compatible to ZBT SRAMs

IDT71V547, MT55L128L36F, and MCM63Z737.

vices IDT71V547, MT55L128L36F, and MCM63Z737

• Supports 66-MHz bus operations with zero wait states

— Data is transferred on every clock

• Internally self-timed output buffer control to eliminate

the need to use OE

• Registered inputs for Flow-Through operation

• Byte Write capability

• 128K x 36 common I/O architecture

• Single 3.3V power supply

All synchronous inputs pass through input registers controlled

by the rising edge of the clock.The clock input is qualified by

the Clock Enable (CEN) signal, which, when deasserted, sus-

pends operation and extends the previous clock cycle. Maxi-

mum access delay from the clock rise is 7.5 ns (117-MHz

device).

• Fast clock-to-output times

— 7.5 ns (for 117-MHz device)

— 8.5 ns (for 100-MHz device)

— 11.0 ns (for 66-MHz device)

— 12.0 ns (for 50-MHz device)

Write operations are controlled by the four Byte Write Select

(BWS_[3:0]) and a Write Enable (WE) input. All writes are con-

ducted with on-chip synchronous self-timed write circuitry.

— 14.0 ns (for 40-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Asynchronous Output Enable

• Standard 100 TQFP and 119 BGA packages

• Burst Capability—linear or interleaved burst order

Low standby power

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank se-

lection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

Logic Block Diagram

CLK

Data-In REG.

ADV/LD

[16:0]

CEN

CONTROL

and WRITE

LOGIC

128KX36

MEMORY

ARRAY

[31:0]

[3:0]

BWS

[3:0]

Mode

Selection Guide

7C1351B-117 7C1351B-100 7C1351B-66 7C1351B-50 7C1351B-40

Maximum Access Time (ns)

7.5

8.5

11.0

12.0

14.0

Maximum Operating Current

(mA)

Commercial

375 mA

350 mA

250 mA

200 mA

175 mA

Maximum CMOS Standby

Current (mA)

5 mA

Cypress Semiconductor Corporation

Document #: 38-05208 Rev. *A

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised November 19, 2002

12 3 4 5 6 7...16

中文翻译

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与CY7C1351B相关器件

型号	品牌	获取价格	描述	数据表
CY7C1351B-100AC	CYPRESS	获取价格	ZBT SRAM, 128KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1351B-100BGC	CYPRESS	获取价格	ZBT SRAM, 128KX36, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1351B-100BGCT	CYPRESS	获取价格	ZBT SRAM, 128KX36, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
CY7C1351B-117AC	CYPRESS	获取价格	ZBT SRAM, 128KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1351B-117ACT	CYPRESS	获取价格	ZBT SRAM, 128KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1351B-117BGC	CYPRESS	获取价格	ZBT SRAM, 128KX36, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1351B-40AC	CYPRESS	获取价格	ZBT SRAM, 128KX36, 14ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1351B-66BGC	CYPRESS	获取价格	ZBT SRAM, 128KX36, 11ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1351F	CYPRESS	获取价格	4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture
CY7C1351F-100AC	CYPRESS	获取价格	4-Mb (128K x 36) Flow-through SRAM with NoBL⑩

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