Datasheet > CY7C1351-66ACT

CY7C1351-66ACT

更新时间： 2024-11-26 20:09:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器内存集成电路
页数	文件大小	规格书
13页	183K
描述
ZBT SRAM, 128KX36, 11ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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技术参数
数据手册

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CY7C1351-66ACT 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	QFP,	针数：	100
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.76
最长访问时间：	11 ns	其他特性：	SELF TIMED WRITE
JESD-30 代码：	R-PQFP-G100	内存密度：	4718592 bit
内存集成电路类型：	ZBT SRAM	内存宽度：	36
功能数量：	1	端子数量：	100
字数：	131072 words	字数代码：	128000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	128KX36
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK
并行/串行：	PARALLEL	认证状态：	Not Qualified
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子位置：	QUAD
Base Number Matches：	1

CY7C1351-66ACT 数据手册

CY7C1351

128Kx36 Flow-Through SRAM with NoBL™ Architecture

Features

Functional Description

Pin compatible and functionally equivalent to ZBT™ de-

vices IDT71V547, MT55L128L36F, and MCM63Z737

• Supports 66-MHz bus operations with zero wait states

— Data is transferred on every clock

•

The CY7C1351 is a 3.3V, 128K by 36 Synchronous

Flow-Through Burst SRAM designed specifically to support

unlimited true back-to-back Read/Write operations without the

insertion of wait states. The CY7C1351 is equipped with the

advanced No Bus Latency™ (NoBL™) logic required to en-

able consecutive Read/Write operations with data being trans-

ferred on every clock cycle. This feature dramatically improves

the throughput of data through the SRAM, especially in sys-

tems that require frequent Write/Read transitions. The

CY7C1351 is pin/functionally compatible to ZBT SRAMs

IDT71V547, MT55L128L36F, and MCM63Z737.

• Internally self-timed output buffer control to eliminate

the need to use OE

• Registered inputs for Flow-Through operation

• Byte Write capability

• 128K x 36 common I/O architecture

• Single 3.3V power supply

All synchronous inputs pass through input registers controlled

by the rising edge of the clock.The clock input is qualified by

the Clock Enable (CEN) signal, which when deasserted sus-

pends operation and extends the previous clock cycle. Maxi-

mum access delay from the clock rise is 11.0 ns (66-MHz

device).

• Fast clock-to-output times

— 11.0 ns (for 66-MHz device)

— 12.0 ns (for 50-MHz device)

— 14.0 ns (for 40-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Asynchronous Output Enable

• JEDEC-standard 100 TQFP package

• Burst Capability—linear or interleaved burst order

Low standby power

Write operations are controlled by the four Byte Write Select

(BWS

) and a Write Enable (WE) input. All writes are con-

[3:0]

ducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE , CE , CE ) and an

asynchronous Output Enable (OE) provide for easy bank se-

lection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

Logic Block Diagram

CLK

Data-In REG.

ADV/LD

A_[16:0]

CEN

CE₁

CE₂

CONTROL

and WRITE

LOGIC

128KX36

MEMORY

ARRAY

DQ_[31:0]

DP_[3:0]

CE₃

BWS

[3:0]

Mode

Selection Guide

7C1351-66

11.0

7C1351-50

7C1351-40

14.0

Maximum Access Time (ns)

12.0

200 mA

5 mA

Maximum Operating Current (mA)

Maximum CMOS Standby Current (mA)

Commercial

250 mA

5 mA

175 mA

5 mA

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation.

ZBT is a trademark of Integrated Device Technology.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

August 9, 1999

12 3 4 5 6 7...13

中文翻译

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与CY7C1351-66ACT相关器件

型号	品牌	获取价格	描述	数据表
CY7C1351B	ETC	获取价格	Memory
CY7C1351B-100AC	CYPRESS	获取价格	ZBT SRAM, 128KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1351B-100BGC	CYPRESS	获取价格	ZBT SRAM, 128KX36, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1351B-100BGCT	CYPRESS	获取价格	ZBT SRAM, 128KX36, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
CY7C1351B-117AC	CYPRESS	获取价格	ZBT SRAM, 128KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1351B-117ACT	CYPRESS	获取价格	ZBT SRAM, 128KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1351B-117BGC	CYPRESS	获取价格	ZBT SRAM, 128KX36, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1351B-40AC	CYPRESS	获取价格	ZBT SRAM, 128KX36, 14ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1351B-66BGC	CYPRESS	获取价格	ZBT SRAM, 128KX36, 11ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1351F	CYPRESS	获取价格	4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture

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