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CY7C1350G-200BGXI PDF预览

CY7C1350G-200BGXI

更新时间： 2024-11-28 09:43:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
15页 336K
描述
4-Mbit (128K x 36) Pipelined SRAM with NoBL? Architecture

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CY7C1350G-200BGXI 数据手册

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CY7C1350G  
4-Mbit (128K x 36) Pipelined SRAM  
with NoBL™ Architecture  
Features  
Functional Description[1]  
• Pin compatible and functionally equivalent to ZBT™  
devices  
The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined  
Burst SRAM designed specifically to support unlimited true  
back-to-back Read/Write operations without the insertion of  
wait states. The CY7C1350G is equipped with the advanced  
No Bus Latency™ (NoBL™) logic required to enable consec-  
utive Read/Write operations with data being transferred on  
every clock cycle. This feature dramatically improves the  
throughput of the SRAM, especially in systems that require  
frequent Write/Read transitions.  
• Internally self-timed output buffer control to eliminate  
the need to use OE  
• Byte Write capability  
• 128K x 36 common I/O architecture  
• 3.3V power supply (VDD  
)
• 2.5V/3.3V I/O power supply (VDDQ  
)
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock. The  
clock input is qualified by the Clock Enable (CEN) signal,  
which, when deasserted, suspends operation and extends the  
previous clock cycle. Maximum access delay from the clock  
rise is 2.6 ns (250-MHz device)  
• Fast clock-to-output times  
— 2.6 ns (for 250-MHz device)  
• Clock Enable (CEN) pin to suspend operation  
• Synchronous self-timed writes  
• Asynchronous output enable (OE)  
Write operations are controlled by the four Byte Write Select  
(BW[A:D]) and a Write Enable (WE) input. All writes are  
conducted with on-chip synchronous self-timed write circuitry.  
• Available in lead-free 100-Pin TQFP package, lead-free  
and non-lead-free 119-Ball BGA package  
• Burst Capability—linear or interleaved burst order  
• “ZZ” Sleep mode option  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. In order to avoid bus  
contention, the output drivers are synchronously tri-stated  
during the data portion of a write sequence.  
Logic Block Diagram  
ADDRESS  
REGISTER 0  
A0, A1, A  
A1  
A0  
A1'  
A0'  
D1  
D0  
Q1  
Q0  
BURST  
LOGIC  
MODE  
C
ADV/LD  
C
CLK  
CEN  
WRITE ADDRESS  
REGISTER 1  
WRITE ADDRESS  
REGISTER 2  
O
O
S
U
D
A
T
U
T
P
T
P
U
T
E
N
S
U
T
ADV/LD  
A
E
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
R
E
G
I
MEMORY  
ARRAY  
B
U
F
S
T
E
E
R
I
DQs  
DQP  
DQP  
DQP  
DQP  
WRITE  
DRIVERS  
BW  
A
B
A
B
C
D
A
M
P
BW  
BW  
C
D
S
T
E
R
S
F
BW  
E
R
S
S
WE  
E
E
N
G
INPUT  
REGISTER 1  
INPUT  
REGISTER 0  
E
E
OE  
READ LOGIC  
CE1  
CE2  
CE3  
SLEEP  
CONTROL  
ZZ  
Note:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05524 Rev. *F  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised July 5, 2006  
1234567...15

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