Datasheet > 存储 > SRAM> CY7C1350G-166AXC

CY7C1350G-166AXC

更新时间： 2024-11-24 22:17:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
15页	299K
描述
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture

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CY7C1350G-166AXC 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100
针数：	100	Reach Compliance Code：	unknown
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.75	Is Samacsys：	N
最长访问时间：	3.5 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	166 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e3
长度：	20 mm	内存密度：	4718592 bit
内存集成电路类型：	ZBT SRAM	内存宽度：	36
湿度敏感等级：	3	功能数量：	1
端子数量：	100	字数：	131072 words
字数代码：	128000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	128KX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP100,.63X.87	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	电源：	2.5/3.3,3.3 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大待机电流：	0.04 A	最小待机电流：	3.14 V
子类别：	SRAMs	最大压摆率：	0.24 mA
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	20	宽度：	14 mm
Base Number Matches：	1

CY7C1350G-166AXC 数据手册

PRELIMINARY

CY7C1350G

4-Mbit (128K x 36) Pipelined SRAM

with NoBL™ Architecture

Functional Description^[1]

Features

• Pin compatible and functionally equivalent to ZBT™

devices

The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined

Burst SRAM designed specifically to support unlimited true

back-to-back Read/Write operations without the insertion of

wait states. The CY7C1350G is equipped with the advanced

No Bus Latency™ (NoBL™) logic required to enable consec-

utive Read/Write operations with data being transferred on

every clock cycle. This feature dramatically improves the

throughput of the SRAM, especially in systems that require

frequent Write/Read transitions.

• Internally self-timed output buffer control to eliminate

the need to use OE

• Byte Write capability

• 128K x 36 common I/O architecture

• Single 3.3V power supply

• 2.5V/3.3V I/O Operation

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal,

which, when deasserted, suspends operation and extends the

previous clock cycle. Maximum access delay from the clock

rise is 2.6 ns (250-MHz device)

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

— 2.6 ns (for 225-MHz device)

— 2.8 ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

— 4.0 ns (for 133-MHz device)

— 4.5 ns (for 100-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Asynchronous output enable (OE)

• Lead-Free 100 TQFP and 119 BGA packages

• Burst Capability—linear or interleaved burst order

• “ZZ” Sleep mode option

Write operations are controlled by the four Byte Write Select

(BW_[A:D]) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

Logic Block Diagram

ADDRESS

A0, A1, A

A1'

A0'

BURST

LOGIC

MODE

ADV/LD

CLK

CEN

WRITE ADDRESS

ADV/LD

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

MEMORY

ARRAY

DQs

DQP

WRITE

DRIVERS

INPUT

READ LOGIC

CE1

CE2

CE3

SLEEP

CONTROL

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05524 Rev. *A

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised October 14, 2004

12 3 4 5 6 7...15

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CY7C1350G-166AXC 替代型号

型号	品牌	替代类型	描述	数据表
CY7C1350F-200AC	CYPRESS	功能相似	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture
CY7C1350G-200AXI	CYPRESS	功能相似	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture
CY7C1350G-166AXI	CYPRESS	功能相似	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture

与CY7C1350G-166AXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1350G-166AXCT	CYPRESS	获取价格	ZBT SRAM, 128KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQ
CY7C1350G-166AXI	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture
CY7C1350G-166BGC	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture
CY7C1350G-166BGI	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture
CY7C1350G-166BGXC	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined SRAM with NoBL? Architecture
CY7C1350G-166BGXI	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined SRAM with NoBL? Architecture
CY7C1350G-200AXC	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture
CY7C1350G-200AXCT	CYPRESS	获取价格	ZBT SRAM, 128KX36, 2.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQ
CY7C1350G-200AXI	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture
CY7C1350G-200BGC	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture

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