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CY7C1350G-100BGXI PDF预览

CY7C1350G-100BGXI

更新时间： 2024-11-25 09:43:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
15页 336K
描述
4-Mbit (128K x 36) Pipelined SRAM with NoBL? Architecture

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CY7C1350G-100BGXI 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：BGA, BGA119,7X17,50
针数：119Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.76最长访问时间：4.5 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：100 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B119
JESD-609代码：e1长度：22 mm
内存密度：4718592 bit内存集成电路类型：ZBT SRAM
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：119
字数：131072 words字数代码：128000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：128KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA119,7X17,50
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：2.4 mm最大待机电流：0.04 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.205 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：20
宽度：14 mmBase Number Matches：1

CY7C1350G-100BGXI 数据手册

 浏览型号CY7C1350G-100BGXI的Datasheet PDF文件第2页浏览型号CY7C1350G-100BGXI的Datasheet PDF文件第3页浏览型号CY7C1350G-100BGXI的Datasheet PDF文件第4页浏览型号CY7C1350G-100BGXI的Datasheet PDF文件第5页浏览型号CY7C1350G-100BGXI的Datasheet PDF文件第6页浏览型号CY7C1350G-100BGXI的Datasheet PDF文件第7页 
CY7C1350G  
4-Mbit (128K x 36) Pipelined SRAM  
with NoBL™ Architecture  
Features  
Functional Description[1]  
• Pin compatible and functionally equivalent to ZBT™  
devices  
The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined  
Burst SRAM designed specifically to support unlimited true  
back-to-back Read/Write operations without the insertion of  
wait states. The CY7C1350G is equipped with the advanced  
No Bus Latency™ (NoBL™) logic required to enable consec-  
utive Read/Write operations with data being transferred on  
every clock cycle. This feature dramatically improves the  
throughput of the SRAM, especially in systems that require  
frequent Write/Read transitions.  
• Internally self-timed output buffer control to eliminate  
the need to use OE  
• Byte Write capability  
• 128K x 36 common I/O architecture  
• 3.3V power supply (VDD  
)
• 2.5V/3.3V I/O power supply (VDDQ  
)
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock. The  
clock input is qualified by the Clock Enable (CEN) signal,  
which, when deasserted, suspends operation and extends the  
previous clock cycle. Maximum access delay from the clock  
rise is 2.6 ns (250-MHz device)  
• Fast clock-to-output times  
— 2.6 ns (for 250-MHz device)  
• Clock Enable (CEN) pin to suspend operation  
• Synchronous self-timed writes  
• Asynchronous output enable (OE)  
Write operations are controlled by the four Byte Write Select  
(BW[A:D]) and a Write Enable (WE) input. All writes are  
conducted with on-chip synchronous self-timed write circuitry.  
• Available in lead-free 100-Pin TQFP package, lead-free  
and non-lead-free 119-Ball BGA package  
• Burst Capability—linear or interleaved burst order  
• “ZZ” Sleep mode option  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. In order to avoid bus  
contention, the output drivers are synchronously tri-stated  
during the data portion of a write sequence.  
Logic Block Diagram  
ADDRESS  
REGISTER 0  
A0, A1, A  
A1  
A0  
A1'  
A0'  
D1  
D0  
Q1  
Q0  
BURST  
LOGIC  
MODE  
C
ADV/LD  
C
CLK  
CEN  
WRITE ADDRESS  
REGISTER 1  
WRITE ADDRESS  
REGISTER 2  
O
O
S
U
D
A
T
U
T
P
T
P
U
T
E
N
S
U
T
ADV/LD  
A
E
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
R
E
G
I
MEMORY  
ARRAY  
B
U
F
S
T
E
E
R
I
DQs  
DQP  
DQP  
DQP  
DQP  
WRITE  
DRIVERS  
BW  
A
B
A
B
C
D
A
M
P
BW  
BW  
C
D
S
T
E
R
S
F
BW  
E
R
S
S
WE  
E
E
N
G
INPUT  
REGISTER 1  
INPUT  
REGISTER 0  
E
E
OE  
READ LOGIC  
CE1  
CE2  
CE3  
SLEEP  
CONTROL  
ZZ  
Note:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05524 Rev. *F  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised July 5, 2006  
1234567...15

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与CY7C1350G-100BGXI相关器件

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CY7C1350G-133AXC CYPRESS

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CY7C1350G-133AXCT CYPRESS

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 		ZBT SRAM, 128KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP
CY7C1350G-133AXI CYPRESS

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 		4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture
CY7C1350G-133AXIT CYPRESS

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 		4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture
CY7C1350G-133BGI CYPRESS

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 		4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture
CY7C1350G-133BGXC CYPRESS

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 		4-Mbit (128K x 36) Pipelined SRAM with NoBL? Architecture
CY7C1350G-133BGXI CYPRESS

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 		4-Mbit (128K x 36) Pipelined SRAM with NoBL? Architecture
CY7C1350G-166AXC CYPRESS

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 		4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture
CY7C1350G-166AXCT CYPRESS

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 		ZBT SRAM, 128KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQ

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