Datasheet > 存储 > SRAM> CY7C1350G-100BGC

CY7C1350G-100BGC

更新时间： 2024-11-24 22:17:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
15页	299K
描述
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture

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CY7C1350G-100BGC 数据手册

PRELIMINARY

CY7C1350G

4-Mbit (128K x 36) Pipelined SRAM

with NoBL™ Architecture

Functional Description^[1]

Features

• Pin compatible and functionally equivalent to ZBT™

devices

The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined

Burst SRAM designed specifically to support unlimited true

back-to-back Read/Write operations without the insertion of

wait states. The CY7C1350G is equipped with the advanced

No Bus Latency™ (NoBL™) logic required to enable consec-

utive Read/Write operations with data being transferred on

every clock cycle. This feature dramatically improves the

throughput of the SRAM, especially in systems that require

frequent Write/Read transitions.

• Internally self-timed output buffer control to eliminate

the need to use OE

• Byte Write capability

• 128K x 36 common I/O architecture

• Single 3.3V power supply

• 2.5V/3.3V I/O Operation

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal,

which, when deasserted, suspends operation and extends the

previous clock cycle. Maximum access delay from the clock

rise is 2.6 ns (250-MHz device)

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

— 2.6 ns (for 225-MHz device)

— 2.8 ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

— 4.0 ns (for 133-MHz device)

— 4.5 ns (for 100-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Asynchronous output enable (OE)

• Lead-Free 100 TQFP and 119 BGA packages

• Burst Capability—linear or interleaved burst order

• “ZZ” Sleep mode option

Write operations are controlled by the four Byte Write Select

(BW_[A:D]) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

Logic Block Diagram

ADDRESS

A0, A1, A

A1'

A0'

BURST

LOGIC

MODE

ADV/LD

CLK

CEN

WRITE ADDRESS

ADV/LD

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

MEMORY

ARRAY

DQs

DQP

WRITE

DRIVERS

INPUT

READ LOGIC

CE1

CE2

CE3

SLEEP

CONTROL

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05524 Rev. *A

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised October 14, 2004

12 3 4 5 6 7...15

中文翻译

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与CY7C1350G-100BGC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1350G-100BGI	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture
CY7C1350G-100BGXC	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined SRAM with NoBL? Architecture
CY7C1350G-100BGXI	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined SRAM with NoBL? Architecture
CY7C1350G-133AXC	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture
CY7C1350G-133AXCT	CYPRESS	获取价格	ZBT SRAM, 128KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP
CY7C1350G-133AXI	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture
CY7C1350G-133AXIT	CYPRESS	获取价格	ZBT SRAM, 128KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP
CY7C1350G-133BGC	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture
CY7C1350G-133BGI	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture
CY7C1350G-133BGXC	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined SRAM with NoBL? Architecture

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