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CY7C1350F-100BGC PDF预览

CY7C1350F-100BGC

更新时间： 2024-11-24 22:07:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
16页 523K
描述
4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture

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中文翻译

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CY7C1350F-100BGC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：14 X 22 MM, 2.40 MM HEIGHT, BGA-119
针数：119Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.83最长访问时间：4.5 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：100 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B119
JESD-609代码：e0长度：22 mm
内存密度：4718592 bit内存集成电路类型：ZBT SRAM
内存宽度：36功能数量：1
端子数量：119字数：131072 words
字数代码：128000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：128KX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA119,7X17,50封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：2.4 mm
最大待机电流：0.04 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.205 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

CY7C1350F-100BGC 数据手册

 浏览型号CY7C1350F-100BGC的Datasheet PDF文件第2页浏览型号CY7C1350F-100BGC的Datasheet PDF文件第3页浏览型号CY7C1350F-100BGC的Datasheet PDF文件第4页浏览型号CY7C1350F-100BGC的Datasheet PDF文件第5页浏览型号CY7C1350F-100BGC的Datasheet PDF文件第6页浏览型号CY7C1350F-100BGC的Datasheet PDF文件第7页 
1CY7C1350F  
CY7C1350F  
4-Mb (128K x 36) Pipelined SRAM with Nobl™ Architecture  
Features  
Functional Description[1]  
• Pin compatible and functionally equivalent to ZBT™  
The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined  
Burst SRAM designed specifically to support unlimited true  
back-to-back Read/Write operations without the insertion of  
wait states. The CY7C1350F is equipped with the advanced  
No Bus Latency™ (NoBL™) logic required to enable consec-  
utive Read/Write operations with data being transferred on  
every clock cycle. This feature dramatically improves the  
throughput of the SRAM, especially in systems that require  
frequent Write/Read transitions.  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock. The  
clock input is qualified by the Clock Enable (CEN) signal,  
which, when deasserted, suspends operation and extends the  
previous clock cycle. Maximum access delay from the clock  
rise is 2.8 ns (200-MHz device)  
devices  
• Internally self-timed output buffer control to eliminate  
the need to use OE  
• Byte Write capability  
• 128K x 36 common I/O architecture  
• Single 3.3V power supply  
• 2.5V/3.3V I/O Operation  
• Fast clock-to-output times  
— 2.6 ns (for 250-MHz device)  
— 2.6 ns (for 225-MHz device)  
— 2.8 ns (for 200-MHz device)  
— 3.5 ns (for 166-MHz device)  
— 4.0 ns (for 133-MHz device)  
— 4.5 ns (for 100-MHz device)  
Write operations are controlled by the four Byte Write Select  
(BW[A:D]) and a Write Enable (WE) input. All writes are  
conducted with on-chip synchronous self-timed write circuitry.  
• Clock Enable (CEN) pin to suspend operation  
• Synchronous self-timed writes  
• Asynchronous output enable (OE)  
• JEDEC-standard 100 TQFP and 119 BGA packages  
• Burst Capability—linear or interleaved burst order  
• “ZZ” Sleep mode option  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output three-state control. In order to avoid bus  
contention, the output drivers are synchronously three-stated  
during the data portion of a write sequence.  
.
Logic Block Diagram  
ADDRESS  
REGISTER 0  
A0, A1, A  
A1  
A0  
A1'  
A0'  
D1  
D0  
Q1  
Q0  
BURST  
LOGIC  
MODE  
C
ADV/LD  
C
CLK  
CEN  
WRITE ADDRESS  
REGISTER 1  
WRITE ADDRESS  
REGISTER 2  
O
U
T
P
O
U
T
P
S
E
N
S
D
A
T
U
T
U
T
ADV/LD  
A
E
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
R
E
G
I
MEMORY  
ARRAY  
B
U
F
S
T
E
E
R
I
DQs  
DQP  
DQP  
DQP  
DQP  
WRITE  
DRIVERS  
BW  
A
B
A
B
C
D
A
M
P
BW  
BW  
C
D
S
T
E
R
S
F
BW  
E
R
S
S
WE  
E
E
N
G
INPUT  
REGISTER 1  
INPUT  
REGISTER 0  
E
E
OE  
READ LOGIC  
CE1  
CE2  
CE3  
SLEEP  
CONTROL  
ZZ  
Note:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05305 Rev. *A  
Revised January 19, 2004  
1234567...16

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