Datasheet > CY7C1350B-133AI

CY7C1350B-133AI

更新时间： 2024-11-25 05:09:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
14页	200K
描述
128Kx36 Pipelined SRAM with NoBL Architecture

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中文翻译

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技术参数
数据手册
替代型号

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CY7C1350B-133AI 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
针数：	100	Reach Compliance Code：	not_compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.51	最长访问时间：	4.2 ns
其他特性：	PIPELINED ARCHITECTURE	最大时钟频率 (fCLK)：	133 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PQFP-G100
JESD-609代码：	e0	长度：	20 mm
内存密度：	4718592 bit	内存集成电路类型：	ZBT SRAM
内存宽度：	36	功能数量：	1
端子数量：	100	字数：	131072 words
字数代码：	128000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	128KX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP100,.63X.87	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大待机电流：	0.005 A
最小待机电流：	3.14 V	子类别：	SRAMs
最大压摆率：	0.3 mA	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	宽度：	14 mm
Base Number Matches：	1

CY7C1350B-133AI 数据手册

350B

PRELIMINARY

CY7C1350B

128Kx36 Pipelined SRAM with NoBL™ Architecture

Features

Functional Description

• Pin compatible and functionally equivalent to ZBT™

devices IDT71V546, MT55L128L36P, and MCM63Z736

• Supports 166-MHz bus operations with zero wait states

— Data is transferred on every clock

The CY7C1350B is a 3.3V, 128K by 36 synchronous-pipelined

Burst SRAM designed specifically to support unlimited true

back-to-back Read/Write operations without the insertion of

wait states. The CY7C1350B is equipped with the advanced

No Bus Latency™ (NoBL™) logic required to enable consec-

utive Read/Write operations with data being transferred on ev-

ery clock cycle. This feature dramatically improves the

throughput of the SRAM, especially in systems that require

frequent Write/Read transitions. The CY7C1350B is pin/func-

• Internally self-timed output buffer control to eliminate

the need to use OE

• Fully registered (inputs and outputs) for pipelined

operation

• Byte Write capability

tionally

compatible

ZBT

SRAMs

IDT71V546,

MT55L128L36P, and MCM63Z736.

• 128K x 36 common I/O architecture

• Single 3.3V power supply

• Fast clock-to-output times

— 3.5 ns (for 166-MHz device)

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal, which

when deasserted suspends operation and extends the previ-

ous clock cycle. Maximum access delay from the clock rise is

3.5 ns (166-MHz device).

— 3.8 ns (for 150-MHz device)

— 4.0 ns (for 143-MHz device)

— 4.2 ns (for 133-MHz device)

— 5.0 ns (for 100-MHz device)

Write operations are controlled by the four Byte Write Select

(BWS_[3:0]) and a Write Enable (WE) input. All writes are con-

ducted with on-chip synchronous self-timed write circuitry.

— 7.0 ns (for 80-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Asynchronous output enable

• JEDEC-standard 100 TQFP package

• Burst Capability—linear or interleaved burst order

• Low standby power (17.325 mW max.)

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank se-

lection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

Logic Block Diagram

CLK

Data-In REG.

ADV/LD

[16:0]

CEN

CONTROL

and WRITE

LOGIC

128Kx36

MEMORY

[31:0]

[3:0]

ARRAY

BWS

[3:0]

MODE

Selection Guide

-166

3.5

400

-150

-143

4.0

350

-133

4.2

300

-100

-80

7.0

200

Maximum Access Time (ns)

3.8

375

5.0

250

Maximum Operating Current (mA)

Commercial

Maximum CMOS Standby Current (mA)

Shaded areas contain advance information.

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation.

ZBT is a trademark of Integrated Device Technology.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05045 Rev. **

Revised September 7, 2001

12 3 4 5 6 7...14

中文翻译

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CY7C1350B-133AI 替代型号

型号	品牌	替代类型	描述	数据表
CY7C1350B-133AC	CYPRESS	完全替代	128Kx36 Pipelined SRAM with NoBL Architecture

与CY7C1350B-133AI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1350B-133AIT	CYPRESS	获取价格	ZBT SRAM, 128KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1350B-143AC	CYPRESS	获取价格	128Kx36 Pipelined SRAM with NoBL Architecture
CY7C1350B-143ACT	CYPRESS	获取价格	ZBT SRAM, 128KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1350B-150AC	CYPRESS	获取价格	128Kx36 Pipelined SRAM with NoBL Architecture
CY7C1350B-166AC	CYPRESS	获取价格	128Kx36 Pipelined SRAM with NoBL Architecture
CY7C1350F	CYPRESS	获取价格	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture
CY7C1350F-100AC	CYPRESS	获取价格	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture
CY7C1350F-100AI	CYPRESS	获取价格	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture
CY7C1350F-100BGC	CYPRESS	获取价格	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture
CY7C1350F-100BGI	CYPRESS	获取价格	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture

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