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CY7C1328F-133AXC PDF预览

CY7C1328F-133AXC

更新时间： 2024-11-27 19:56:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
17页 353K
描述
Cache SRAM, 256KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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CY7C1328F-133AXC 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFP包装说明：LQFP,
针数：100Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.66最长访问时间：4 ns
其他特性：PIPELINED ARCHITECTUREJESD-30 代码：R-PQFP-G100
JESD-609代码：e3长度：20 mm
内存密度：4718592 bit内存集成电路类型：CACHE SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：100
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：256KX18
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：14 mm
Base Number Matches：1

CY7C1328F-133AXC 数据手册

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CY7C1328F  
4-Mb(256Kx18)PipelinedDCDSyncSRAM  
Features  
Functional Description[1]  
• Registered inputs and outputs for pipelined operation  
• Optimal for performance (Double-Cycle deselect)  
— Depth expansion without wait state  
The CY7C1328F SRAM integrates 262,144 x 18 SRAM cells  
with advanced synchronous peripheral circuitry and a two-bit  
counter for internal burst operation. All synchronous inputs are  
gated by registers controlled by a positive-edge-triggered  
Clock Input (CLK). The synchronous inputs include all  
addresses, all data inputs, address-pipelining Chip Enable  
• 256K × 18-bit common I/O architecture  
• 3.3V –5% and +10% core power supply (VDD  
)
(
), depth-expansion Chip Enables (CE and  
), Burst  
CE3  
CE1  
2
• 3.3V / 2.5V I/O supply (VDDQ  
)
Control inputs (  
,
,
), Write Enables  
). Asynchronous  
and  
ADV  
ADSC ADSP  
(
, and  
BW[A:B]  
), and Global Write (  
BWE GW  
• Fast clock-to-output times  
inputs include the Output Enable ( ) and the ZZ pin.  
OE  
— 2.6 ns (for 250-MHz device)  
— 2.6 ns (for 225-MHz device)  
— 2.8 ns (for 200-MHz device)  
— 3.5 ns (for 166-MHz device)  
— 4.0 ns (for 133-MHz device)  
— 4.5 ns (for 100-MHz device)  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (  
) or  
ADSP  
Address Strobe Controller (  
) are active. Subsequent  
ADSC  
burst addresses can be internally generated as controlled by  
the Advance pin ( ).  
ADV  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed Write cycle.This part supports Byte Write  
operations (see Pin Descriptions and Truth Table for further  
details). Write cycles can be one to two bytes wide as  
• Provide high-performance 3-1-1-1 access rate  
• User-selectable burst counter supporting Intel  
controlled by the byte write control inputs.  
active  
GW  
LOW  
Pentiuminterleaved or linear burst sequences  
This device incorporates an  
causes all bytes to be written.  
additional pipelined enable register which delays turning off  
the output buffers an additional cycle when a deselect is  
executed.This feature allows depth expansion without penal-  
izing system performance.  
• Separate processor and controller address strobes  
• Synchronous self-timed writes  
• Asynchronous Output Enable  
• JEDEC-standard 100-pin TQFP package and pinout  
• “ZZ” Sleep Mode option  
The CY7C1328F operates from a +3.3V core power supply  
while all outputs operate with a +3.3V or a +2.5V supply. All  
inputs and outputs are JEDEC-standard JESD8-5-compatible.  
Selection Guide  
250 MHz  
2.6  
225 MHz  
2.6  
200 MHz  
2.8  
166 MHz  
3.5  
133 MHz  
4.0  
100 MHz  
4.5  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
325  
40  
290  
40  
265  
40  
240  
40  
225  
40  
205  
40  
mA  
mA  
Shaded areas contain advance information.  
Please contact your local Cypress sales representative for availability of these parts.  
Note:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05220 Rev. *A  
Revised January 19, 2004  
1234567...17

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 		4-Mb (256K x 18) Pipelined DCD Sync SRAM
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 		Cache SRAM, 256KX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
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 		4-Mb (256K x 18) Pipelined DCD Sync SRAM
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 		4-Mb (256K x 18) Pipelined DCD Sync SRAM
CY7C1328F-200AXC CYPRESS

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 		Cache SRAM, 256KX18, 2.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1328F-200AXI CYPRESS

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 		Cache SRAM, 256KX18, 2.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1328F-225AC CYPRESS

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 		4-Mb (256K x 18) Pipelined DCD Sync SRAM
CY7C1328F-225AI CYPRESS

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 		4-Mb (256K x 18) Pipelined DCD Sync SRAM

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