Datasheet > CY7C1327F-200AXI

CY7C1327F-200AXI

更新时间： 2024-11-20 03:03:59

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
17页	614K
描述
Cache SRAM, 256KX18, 2.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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CY7C1327F-200AXI 数据手册

CY7C1327F

4-Mb (256K x 18) Pipelined Sync SRAM

Features

Functional Description^[1]

• Registered inputs and outputs for pipelined operation

• 256K ×18 common I/O architecture

• 3.3V core power supply

• 3.3V / 2.5V I/O operation

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

— 2.6 ns (for 225-MHz device)

— 2.8 ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

The CY7C1327F SRAM integrates 262,144 x 18 SRAM cells

with advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(

), depth-expansion Chip Enables (CE and

), Burst

CE₃

CE₁

Control inputs (

and

ADSC ADSP

), Write Enables

ADV

(

, and

), and Global Write (

BWE

). Asynchronous

BW_[A:B]

inputs include the Output Enable ( ) and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (

) or

ADSP

Address Strobe Controller (

) are active. Subsequent

ADSC

— 4.0 ns (for 133-MHz device)

— 4.5 ns (for 100-MHz device)

burst addresses can be internally generated as controlled by

the Advance pin ( ).

ADV

• Provide high-performance 3-1-1-1 access rate

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two bytes wide as

• User-selectable burst counter supporting Intel^

Pentium interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

controlled by the byte write control inputs.

when active

causes all bytes to be written.

LOW

The CY7C1327F operates from a +3.3V core power supply

while all outputs also operate with a +3.3V or a +2.5V supply.

• Offered in JEDEC-standard 100-pin TQFP and 119 Ball

All

inputs

and

outputs

are

JEDEC-standard

BGA packages.

JESD8-5-compatible.

• “ZZ” Sleep Mode Option

Logic Block Diagram

ADDRESS

A0, A1, A

A[1:0]

MODE

ADV

CLK

BURST

COUNTER AND

LOGIC

CLR

ADSC

ADSP

DQB,DQP

WRITE REGISTER

WRITE DRIVER

OUTPUT

BUFFERS

DQs

DQP

OUTPUT

REGISTERS

SENSE

AMPS

MEMORY

ARRAY

DQA,DQP

WRITE REGISTER

WRITE DRIVER

BWE

INPUT

REGISTERS

ENABLE

CE1

CE2

PIPELINED

ENABLE

CE3

SLEEP

CONTROL

Note:

1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05216 Rev. *B

Revised December 12, 2003

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与CY7C1327F-200AXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1327F-200BGC	CYPRESS	获取价格	4-Mb (256K x 18) Pipelined Sync SRAM
CY7C1327F-200BGI	CYPRESS	获取价格	4-Mb (256K x 18) Pipelined Sync SRAM
CY7C1327F-225AC	CYPRESS	获取价格	4-Mb (256K x 18) Pipelined Sync SRAM
CY7C1327F-225AI	CYPRESS	获取价格	4-Mb (256K x 18) Pipelined Sync SRAM
CY7C1327F-225AXC	CYPRESS	获取价格	Cache SRAM, 256KX18, 2.6ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1327F-225AXI	CYPRESS	获取价格	Cache SRAM, 256KX18, 2.6ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1327F-225BGC	CYPRESS	获取价格	4-Mb (256K x 18) Pipelined Sync SRAM
CY7C1327F-225BGI	CYPRESS	获取价格	4-Mb (256K x 18) Pipelined Sync SRAM
CY7C1327F-250AC	CYPRESS	获取价格	4-Mb (256K x 18) Pipelined Sync SRAM
CY7C1327F-250AI	CYPRESS	获取价格	4-Mb (256K x 18) Pipelined Sync SRAM

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