Datasheet > 存储 > SRAM> CY7C1316BV18-167BZC

CY7C1316BV18-167BZC

更新时间： 2024-11-23 23:13:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器双倍数据速率时钟
页数	文件大小	规格书
24页	258K
描述
18-Mbit DDR-II SRAM 2-Word Burst Architecture

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

CY7C1316BV18-167BZC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.32
Is Samacsys：	N	最长访问时间：	0.5 ns
其他特性：	PIPELINED ARCHITECTURE	最大时钟频率 (fCLK)：	167 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e0	长度：	15 mm
内存密度：	16777216 bit	内存集成电路类型：	DDR SRAM
内存宽度：	8	湿度敏感等级：	3
功能数量：	1	端子数量：	165
字数：	2097152 words	字数代码：	2000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	2MX8
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	220
电源：	1.5/1.8,1.8 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最大待机电流：	0.2 A
最小待机电流：	1.7 V	子类别：	SRAMs
最大压摆率：	0.45 mA	最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	13 mm	Base Number Matches：	1

CY7C1316BV18-167BZC 数据手册

浏览型号CY7C1316BV18-167BZC的Datasheet PDF文件第2页

浏览型号CY7C1316BV18-167BZC的Datasheet PDF文件第3页

浏览型号CY7C1316BV18-167BZC的Datasheet PDF文件第4页

浏览型号CY7C1316BV18-167BZC的Datasheet PDF文件第5页

浏览型号CY7C1316BV18-167BZC的Datasheet PDF文件第6页

CY7C1316BV18

CY7C1916BV18

CY7C1318BV18

CY7C1320BV18

PRELIMINARY

18-Mbit DDR-II SRAM 2-Word

Burst Architecture

Features

Functional Description

• 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)

• 250-MHz clock for high bandwidth

The CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and

CY7C1320BV18 are 1.8V Synchronous Pipelined SRAM

equipped with DDR-II architecture. The DDR-II consists of an

SRAM core with advanced synchronous peripheral circuitry

and a 1-bit burst counter. Addresses for Read and Write are

latched on alternate rising edges of the input (K) clock. Write

data is registered on the rising edges of both K and K. Read

data is driven on the rising edges of C and C if provided, or on

the rising edge of K and K if C/C are not provided. Each

address location is associated with two 8-bit words in the case

of CY7C1316BV18 and two 9-bit words in the case of

CY7C1916BV18 that burst sequentially into or out of the

device. The burst counter always starts with a “0” internally in

the case of CY7C1316BV18 and CY7C1916BV18. On

CY7C1318BV18 and CY7C1320BV18, the burst counter

takes in the least significant bit of the external address and

bursts two 18-bit words in the case of CY7C1318BV18 and two

36-bit words in the case of CY7C1320BV18 sequentially into

or out of the device.

• 2-Word burst for reducing address bus frequency

• Double Data Rate (DDR) interfaces

(data transferred at 500 MHz) @ 250 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C) account for clock skew

and flight time mismatching

• Echo clocks (CQ and CQ) simplify data capture in

high-speed systems

• Synchronous internally self-timed writes

• 1.8V core power supply with HSTL inputs and outputs

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–V_DD

)

Asynchronous inputs include impedance match (ZQ).

Synchronous data outputs (Q, sharing the same physical pins

as the data inputs D) are tightly matched to the two output echo

clocks CQ/CQ, eliminating the need for separately capturing

data from each individual DDR SRAM in the system design.

Output data clocks (C/C) enable maximum system clocking

and data synchronization flexibility.

• 15 x 17 x 1.4 mm 1.0-mm pitch fBGA package,

165 ball (11x15 matrix)

• JTAG 1149.1 compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

Configurations

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

CY7C1316BV18 – 2M x 8

CY7C1916BV18 – 2M x 9

CY7C1318BV18 – 1M x 18

CY7C1320BV18 – 512K x 36

Selection Guide

250 MHz

250

200 MHz

200

167 MHz

167

Unit

MHz

Maximum Operating Frequency

Maximum Operating Current

TBD

Shaded areas contain advance information.

Cypress Semiconductor Corporation

Document Number: 38-05621 Rev. **

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised July 26, 2004

12 3 4 5 6 7...24

中文翻译

下载PDF

与CY7C1316BV18-167BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1316BV18-167BZI	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1316BV18-167BZXC	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1316BV18-167BZXI	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1316BV18-200BZC	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1316BV18-200BZI	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1316BV18-200BZXC	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1316BV18-200BZXI	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1316BV18-250BZC	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1316BV18-250BZI	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1316BV18-250BZXC	CYPRESS	获取价格	18-Mbit DDR-II SRAM 2-Word Burst Architecture

与CY7C1316BV18-167BZC相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

38
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

30
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

58
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

54

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1316BV18-167BZC

CY7C1316BV18-167BZC 技术参数

CY7C1316BV18-167BZC 数据手册

与CY7C1316BV18-167BZC相关器件

与CY7C1316BV18-167BZC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1316BV18-167BZC

CY7C1316BV18-167BZC 技术参数

CY7C1316BV18-167BZC 数据手册

与CY7C1316BV18-167BZC相关器件

与CY7C1316BV18-167BZC相关文章

您还可以找

您在本页遇到什么问题？