Datasheet > 存储 > SRAM> CY7C1212F-133ACT

CY7C1212F-133ACT

更新时间： 2024-11-09 13:07:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
15页	318K
描述
Cache SRAM, 64KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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技术参数
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CY7C1212F-133ACT 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP,	针数：	100
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.84
Is Samacsys：	N	最长访问时间：	4 ns
其他特性：	PIPELINED ARCHITECTURE	JESD-30 代码：	R-PQFP-G100
JESD-609代码：	e0	长度：	20 mm
内存密度：	1179648 bit	内存集成电路类型：	CACHE SRAM
内存宽度：	18	功能数量：	1
端子数量：	100	字数：	65536 words
字数代码：	64000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	64KX18	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	TIN LEAD	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
宽度：	14 mm	Base Number Matches：	1

CY7C1212F-133ACT 数据手册

CY7C1212F

1-Mbit (64K x 18) Pipelined Sync SRAM

Features

Functional Description^[1]

• Registered inputs and outputs for pipelined operation

• 64K × 18 common I/O architecture

• 3.3V core power supply

• 3.3V I/O operation

• Fast clock-to-output times

The CY7C1212F SRAM integrates 65,536 x 18 SRAM cells

with advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(

), depth-expansion Chip Enables (CE and

), Burst

CE₃

CE₁

— 3.5 ns (for 166-MHz device)

— 4.0 ns (for 133-MHz device)

Control inputs (

and

ADSC ADSP

), Write Enables

ADV

(

, and

), and Global Write (

BWE

). Asynchronous

BW_[A:B]

inputs include the Output Enable ( ) and the ZZ pin.

• Provide high-performance 3-1-1-1 access rate

Addresses and chip enables are registered at rising edge of

• User-selectable burst counter supporting Intel^

clock when either Address Strobe Processor (

) or

ADSP

Pentium^®interleaved or linear burst sequences

Address Strobe Controller (

) are active. Subsequent

ADSC

burst addresses can be internally generated as controlled by

the Advance pin ( ).

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Offered in JEDEC-standard 100-pin TQFP package

• “ZZ” Sleep Mode Option

ADV

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two bytes wide as

controlled by the Byte Write control inputs.

when active

causes all bytes to be written.

LOW

The CY7C1212F operates from a +3.3V core power supply

while all outputs may operate with a +3.3V supply. All inputs

and outputs are JEDEC-standard JESD8-5-compatible.

Logic Block Diagram

ADDRESS

A0, A1, A

A[1:0]

MODE

ADV

CLK

BURST

COUNTER

AND

LOGIC

CLR

ADSC

ADSP

DQB,DQP

WRITE REGISTER

WRITE DRIVER

OUTPUT

BUFFERS

DQs

DQP

OUTPUT

REGISTERS

SENSE

AMPS

MEMORY

ARRAY

DQA,DQP

WRITE REGISTER

WRITE DRIVER

BWE

INPUT

REGISTERS

ENABLE

CE1

CE2

PIPELINED

ENABLE

CE3

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05423 Rev. *A

Revised April 7, 2004

12 3 4 5 6 7...15

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与CY7C1212F-133ACT相关器件

型号	品牌	获取价格	描述	数据表
CY7C1212F-133AXC	CYPRESS	获取价格	Cache SRAM, 64KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.4 MM HEIGHT, PLASTIC, TQFP-100
CY7C1212H	CYPRESS	获取价格	1-Mbit (64K x 18) Pipelined Sync SRAM
CY7C1212H-100AXC	CYPRESS	获取价格	1-Mbit (64K x 18) Pipelined Sync SRAM
CY7C1212H-100AXI	CYPRESS	获取价格	1-Mbit (64K x 18) Pipelined Sync SRAM
CY7C1212H-133AXC	CYPRESS	获取价格	1-Mbit (64K x 18) Pipelined Sync SRAM
CY7C1212H-133AXI	CYPRESS	获取价格	1-Mbit (64K x 18) Pipelined Sync SRAM
CY7C1214F	CYPRESS	获取价格	1-Mb (32K x 32) Flow-Through Sync SRAM
CY7C1214F-100AC	CYPRESS	获取价格	1-Mb (32K x 32) Flow-Through Sync SRAM
CY7C1214F-100ACT	CYPRESS	获取价格	Cache SRAM, 32KX32, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1214F-117AC	CYPRESS	获取价格	Standard SRAM, 32KX32, 7.5ns, CMOS, PQFP100

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