Datasheet > CY7C11771KV18

CY7C11771KV18

更新时间： 2024-11-07 09:43:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器双倍数据速率
页数	文件大小	规格书
26页	749K
描述
18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C11771KV18 数据手册

CY7C11661KV18, CY7C11771KV18

CY7C11681KV18, CY7C11701KV18

18-Mbit DDR II+ SRAM Two-Word Burst

Architecture (2.5 Cycle Read Latency)

18-Mbit DDR II+ SRAM Two-Burst Architecture (2.5 Cycle Read Latency)

Features

Functional Description

■ 18-Mbit density (2 M × 8, 2 M × 9, 1 M × 18, 512 K × 36)

■ 550 MHz clock for high bandwidth

The CY7C11661KV18, CY7C11771KV18, CY7C11681KV18,

and CY7C11701KV18 are 1.8 V Synchronous Pipelined SRAMs

equipped with DDR II+ architecture. The DDR II+ consists of an

SRAM core with advanced synchronous peripheral circuitry.

Addresses for read and write are latched on alternate rising

edges of the input (K) clock. Write data is registered on the rising

edges of both K and K. Read data is driven on the rising edges

of K and K. Each address location is associated with two 8-bit

words (CY7C11661KV18), 9-bit words (CY7C11771KV18),

■ 2-word burst for reducing address bus frequency

■ Double data rate (DDR) interfaces

(data transferred at 1100 MHz) at 550 MHz

■ Available in 2.5 clock cycle latency

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

18-bit

words

(CY7C11681KV18),

36-bit

words

(CY7C11701KV18) that burst sequentially into or out of the

device.

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design.

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

■ DDR II+ operates with 2.5 cycle read latency when DOFF is

asserted HIGH

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ OperatessimilartoDDRIdevicewith1cyclereadlatencywhen

DOFF is asserted LOW

[1]

■ Core V_DD= 1.8 V ± 0.1 V; I/O V_DDQ= 1.4 V to V_DD

❐ Supports both 1.5 V and 1.8 V I/O supply

Table 1. Selection Guide

550 500 450 400

Description

Unit

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-Ball FBGA package (13 × 15 × 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

MHz MHz MHz MHz

Maximum operating

frequency

550 500 450 400 MHz

Maximum operating

current

x8 740 690 630 580 mA

x9 740 690 630 580

x18 760 700 650 590

x36 970 890 820 750

■ Phase-locked loop (PLL) for accurate data placement

Configurations

With Read cycle latency of 2.5 cycles:

CY7C11661KV18 – 2 M × 8

CY7C11771KV18 – 2 M × 9

CY7C11681KV18 – 1 M × 18

CY7C11701KV18 – 512 K × 36

Note

1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V

= 1.4 V to V

DDQ

Cypress Semiconductor Corporation

Document Number: 001-53199 Rev. *I

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 31, 2011

[+] Feedback

12 3 4 5 6 7...26

中文翻译

下载PDF

与CY7C11771KV18相关器件

型号	品牌	获取价格	描述	数据表
CY7C1177KV18	CYPRESS	获取价格	18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1177V18	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1177V18-300BZC	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1177V18-300BZI	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1177V18-300BZXC	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1177V18-300BZXI	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1177V18-333BZC	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1177V18-333BZI	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1177V18-333BZXC	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1177V18-333BZXI	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)

与CY7C11771KV18相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

16
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

14
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

37
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

35

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C11771KV18

CY7C11771KV18 数据手册

与CY7C11771KV18相关器件

与CY7C11771KV18相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C11771KV18

CY7C11771KV18 数据手册

与CY7C11771KV18相关器件

与CY7C11771KV18相关文章

您还可以找

您在本页遇到什么问题？