Datasheet > 存储 > SRAM> CY7C11681KV18-450BZXC

CY7C11681KV18-450BZXC

更新时间： 2024-11-07 09:43:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器双倍数据速率时钟
页数	文件大小	规格书
26页	749K
描述
18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)

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CY7C11681KV18-450BZXC 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
针数：	165	Reach Compliance Code：	unknown
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.75	Is Samacsys：	N
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	450 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e1
长度：	15 mm	内存密度：	18874368 bit
内存集成电路类型：	DDR SRAM	内存宽度：	18
湿度敏感等级：	3	功能数量：	1
端子数量：	165	字数：	1048576 words
字数代码：	1000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	1MX18	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	电源：	1.5/1.8,1.8 V
认证状态：	Not Qualified	座面最大高度：	1.4 mm
最大待机电流：	0.34 A	最小待机电流：	1.7 V
子类别：	SRAMs	最大压摆率：	0.65 mA
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	20	宽度：	13 mm
Base Number Matches：	1

CY7C11681KV18-450BZXC 数据手册

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CY7C11661KV18, CY7C11771KV18

CY7C11681KV18, CY7C11701KV18

18-Mbit DDR II+ SRAM Two-Word Burst

Architecture (2.5 Cycle Read Latency)

18-Mbit DDR II+ SRAM Two-Burst Architecture (2.5 Cycle Read Latency)

Features

Functional Description

■ 18-Mbit density (2 M × 8, 2 M × 9, 1 M × 18, 512 K × 36)

■ 550 MHz clock for high bandwidth

The CY7C11661KV18, CY7C11771KV18, CY7C11681KV18,

and CY7C11701KV18 are 1.8 V Synchronous Pipelined SRAMs

equipped with DDR II+ architecture. The DDR II+ consists of an

SRAM core with advanced synchronous peripheral circuitry.

Addresses for read and write are latched on alternate rising

edges of the input (K) clock. Write data is registered on the rising

edges of both K and K. Read data is driven on the rising edges

of K and K. Each address location is associated with two 8-bit

words (CY7C11661KV18), 9-bit words (CY7C11771KV18),

■ 2-word burst for reducing address bus frequency

■ Double data rate (DDR) interfaces

(data transferred at 1100 MHz) at 550 MHz

■ Available in 2.5 clock cycle latency

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

18-bit

words

(CY7C11681KV18),

36-bit

words

(CY7C11701KV18) that burst sequentially into or out of the

device.

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design.

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

■ DDR II+ operates with 2.5 cycle read latency when DOFF is

asserted HIGH

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ OperatessimilartoDDRIdevicewith1cyclereadlatencywhen

DOFF is asserted LOW

[1]

■ Core V_DD= 1.8 V ± 0.1 V; I/O V_DDQ= 1.4 V to V_DD

❐ Supports both 1.5 V and 1.8 V I/O supply

Table 1. Selection Guide

550 500 450 400

Description

Unit

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-Ball FBGA package (13 × 15 × 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

MHz MHz MHz MHz

Maximum operating

frequency

550 500 450 400 MHz

Maximum operating

current

x8 740 690 630 580 mA

x9 740 690 630 580

x18 760 700 650 590

x36 970 890 820 750

■ Phase-locked loop (PLL) for accurate data placement

Configurations

With Read cycle latency of 2.5 cycles:

CY7C11661KV18 – 2 M × 8

CY7C11771KV18 – 2 M × 9

CY7C11681KV18 – 1 M × 18

CY7C11701KV18 – 512 K × 36

Note

1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V

= 1.4 V to V

DDQ

Cypress Semiconductor Corporation

Document Number: 001-53199 Rev. *I

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 31, 2011

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与CY7C11681KV18-450BZXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1168KV18	CYPRESS	获取价格	18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1168KV18-400BZC	CYPRESS	获取价格	18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1168KV18-400BZXC	CYPRESS	获取价格	18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1168KV18-400BZXC	INFINEON	获取价格	DDR-II+ CIO
CY7C1168KV18-450BZC	CYPRESS	获取价格	18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1168KV18-450BZXC	CYPRESS	获取价格	18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1168KV18-550BZXC	CYPRESS	获取价格	18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1168KV18-550BZXC	INFINEON	获取价格	DDR-II+ CIO
CY7C1168V18	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1168V18-300BZC	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)

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