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CY7C109B-15ZXC PDF预览

CY7C109B-15ZXC

更新时间： 2024-11-20 02:51:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
10页 379K
描述
128K x 8 Static RAM

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CY7C109B-15ZXC 数据手册

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CY7C109B  
CY7C1009B  
128K x 8 Static RAM  
Features  
Functional Description[1]  
• High speed  
The CY7C109B/CY7C1009B is a high-performance CMOS  
static RAM organized as 131,072 words by 8 bits. Easy  
memory expansion is provided by an active LOW Chip Enable  
(CE1), an active HIGH Chip Enable (CE2), an active LOW  
Output Enable (OE), and tri-state drivers. Writing to the device  
is accomplished by taking Chip Enable One (CE1) and Write  
Enable (WE) inputs LOW and Chip Enable Two (CE2) input  
HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then  
written into the location specified on the address pins (A0  
through A16).  
— tAA = 12 ns  
• Low active power  
— 495 mW (max.)  
• Low CMOS standby power  
— 11 mW (max.) (L Version)  
• 2.0V Data Retention  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE1, CE2, and OE options  
Reading from the device is accomplished by taking Chip  
Enable One (CE1) and Output Enable (OE) LOW while forcing  
Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under  
these conditions, the contents of the memory location  
specified by the address pins will appear on the I/O pins.  
• CY7C109B is available in standard 400-mil-wide SOJ  
and 32-pin TSOP type I packages. The CY7C1009B is  
available in a 300-mil-wide SOJ package  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE1  
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or  
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).  
CY7C109B is available in standard 400-mil-wide SOJ and 32-  
pin TSOP type I packages. The CY7C1009B is available in a  
300-mil-wide SOJ package. The CY7C109B and CY7C1009B  
are functionally equivalent in all other respects  
Pin Configurations[2]  
Logic Block Diagram  
SOJ  
Top View  
V
NC  
32  
31  
30  
1
CC  
A
16  
A
15  
CE  
2
3
4
A
14  
2
A
12  
29  
28  
WE  
5
A
7
A
6
A
5
A
A
A
13  
8
27  
26  
6
7
9
25  
24  
23  
22  
21  
A
A
8
9
10  
11  
12  
13  
A
4
3
11  
I/O  
0
OE  
A
A
A
10  
INPUT BUFFER  
2
1
CE  
I/O  
I/O  
1
7
6
I/O  
I/O  
A
I/O  
1
0
0
A
0
20  
19  
A
1
I/O  
I/O  
GND  
I/O  
1
5
14  
15  
16  
2
A
2
I/O  
I/O  
2
18  
17  
4
3
A
3
4
A
I/O  
I/O  
I/O  
128K x 8  
ARRAY  
3
4
5
A
A
11  
1
2
32  
31  
OE  
5
6
A
A
A
A
9
8
10  
3
4
5
6
7
8
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
CE  
I/O  
A
7
8
A
13  
7
A
WE  
I/O  
I/O  
I/O  
I/O  
6
5
CE  
2
A
15  
TSOP I  
4
3
V
Top View  
CC  
I/O  
6
7
NC  
9
GND  
(not to scale)  
POWER  
DOWN  
COLUMN  
DECODER  
A
I/O  
10  
11  
12  
13  
14  
15  
16  
16  
2
CE  
2
WE  
1
I/O  
1
A
CE  
14  
A
I/O  
I/O  
12  
0
A
A
0
7
A
A
6
1
A
2
OE  
A
A
5
4
A
3
Note:  
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.  
2. NC pins are not connected on the die.  
Cypress Semiconductor Corporation  
Document #: 38-05038 Rev. *C  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised August 3, 2006  
[+] Feedback  
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