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CY7C109-15ZI PDF预览

CY7C109-15ZI

更新时间： 2023-07-15 00:00:00
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管
页数 文件大小 规格书
11页 207K
描述
Standard SRAM, 128KX8, 15ns, CMOS, PDSO32, TSOP1-32

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CY7C109-15ZI 数据手册

 浏览型号CY7C109-15ZI的Datasheet PDF文件第2页浏览型号CY7C109-15ZI的Datasheet PDF文件第3页浏览型号CY7C109-15ZI的Datasheet PDF文件第4页浏览型号CY7C109-15ZI的Datasheet PDF文件第5页浏览型号CY7C109-15ZI的Datasheet PDF文件第6页浏览型号CY7C109-15ZI的Datasheet PDF文件第7页 
CY7C109  
CY7C1009  
128K x 8 Static RAM  
able (OE), and three-state drivers. Writing to the device is ac-  
Features  
complished by taking Chip Enable One (CE ) and Write En-  
1
• High speed  
able (WE) inputs LOW and Chip Enable Two (CE ) input HIGH.  
2
Data on the eight I/O pins (I/O through I/O ) is then written  
0
7
— t = 10 ns  
AA  
into the location specified on the address pins (A through  
0
• Low active power  
A
).  
16  
— 1017 mW (max., 12 ns)  
Reading from the device is accomplished by taking Chip En-  
• Low CMOS standby power  
able One (CE ) and Output Enable (OE) LOW while forcing  
1
Write Enable (WE) and Chip Enable Two (CE ) HIGH. Under  
these conditions, the contents of the memory location speci-  
fied by the address pins will appear on the I/O pins.  
— 55 mW (max.), 4 mW (Low-power version)  
• 2.0V Data Retention (Low-power version)  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
2
The eight input/output pins (I/O through I/O ) are placed in a  
0
7
high-impedance state when the device is deselected (CE  
1
• Easy memory expansion with CE , CE , and OE options  
1
2
HIGH or CE LOW), the outputs are disabled (OE HIGH), or  
2
during a write operation (CE LOW, CE HIGH, and WE LOW).  
1
2
Functional Description  
The CY7C109 is available in standard 400-mil-wide SOJ and  
32-pin TSOP type I packages. The CY7C1009 is available in  
a 300-mil-wide SOJ package. The CY7C1009 and CY7C109  
are functionally equivalent in all other respects.  
The CY7C109 / CY7C1009 is a high-performance CMOS stat-  
ic RAM organized as 131,072 words by 8 bits. Easy memory  
expansion is provided by an active LOW Chip Enable (CE ),  
1
an active HIGH Chip Enable (CE ), an active LOW Output En-  
2
Logic Block Diagram  
Pin Configurations  
SOJ  
Top View  
V
NC  
32  
31  
30  
1
CC  
A
16  
A
14  
A
12  
A
15  
2
3
4
CE  
2
29  
28  
WE  
5
A
A
A
A
7
13  
27  
26  
A
6
6
8
A
5
7
9
25  
24  
23  
22  
21  
A
A
3
8
9
10  
11  
12  
13  
4
A
11  
OE  
I/O  
A
A
10  
2
0
A
1
CE  
INPUT BUFFER  
1
I/O  
7
A
0
I/O  
I/O  
I/O  
0
I/O  
1
I/O  
2
I/O  
6
20  
19  
1
2
A
0
I/O  
5
14  
15  
16  
A
1
I/O  
I/O  
4
18  
17  
A
2
GND  
3
109–2  
A
3
4
A
A
A
WE  
CE  
1
2
32  
31  
11  
OE  
I/O  
I/O  
I/O  
3
4
5
512 x 256 x 8  
ARRAY  
A
A
A
9
10  
5
6
3
4
5
6
7
8
A
8
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
CE  
I/O  
A
13  
7
A
7
8
I/O  
6
I/O  
5
A
2
A
15  
I/O  
I/O  
TSOP I  
4
V
Top View  
CC  
3
NC  
9
GND  
(not to scale)  
A
16  
I/O  
2
I/O  
I/O  
10  
11  
12  
13  
14  
15  
16  
6
7
POWER  
DOWN  
I/O  
1
COLUMN  
DECODER  
A
14  
CE  
2
1
CE  
A
I/O  
12  
0
A
A
6
A
A
A
0
7
WE  
A
1
A
2
5
109–1  
A
3
OE  
4
109–3  
Selection Guide  
7C109-10  
7C109-12  
7C109-15  
7C109-20  
7C109-25  
7C109-35  
7C1009-10 7C1009-12 7C1009-15 7C1009-20 7C1009-25 7C1009-35  
Maximum Access Time (ns)  
Maximum Operating Current (mA)  
Maximum CMOS Standby Current (mA)  
Maximum CMOS Standby Current (mA)  
Low-Power Version  
10  
195  
10  
2
12  
185  
10  
2
15  
155  
10  
2
20  
140  
10  
25  
135  
10  
35  
125  
10  
—
—
—
Shaded areas contain preliminary information.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
September 7, 1999  
1234567...11

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