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CY7C1061GE30-10BV1XIT PDF预览

CY7C1061GE30-10BV1XIT

更新时间： 2024-11-19 15:36:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
25页 576K
描述
Standard SRAM, 1MX16, 10ns, CMOS, PBGA48, VFBGA-48

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CY7C1061GE30-10BV1XIT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：VFBGA,
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.79
最长访问时间：10 nsJESD-30 代码：R-PBGA-B48
长度：8 mm内存密度：16777216 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
功能数量：1端子数量：48
字数：1048576 words字数代码：1000000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：1MX16
封装主体材料：PLASTIC/EPOXY封装代码：VFBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
座面最大高度：1 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.2 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：0.75 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：6 mm
Base Number Matches：1

CY7C1061GE30-10BV1XIT 数据手册

 浏览型号CY7C1061GE30-10BV1XIT的Datasheet PDF文件第2页浏览型号CY7C1061GE30-10BV1XIT的Datasheet PDF文件第3页浏览型号CY7C1061GE30-10BV1XIT的Datasheet PDF文件第4页浏览型号CY7C1061GE30-10BV1XIT的Datasheet PDF文件第5页浏览型号CY7C1061GE30-10BV1XIT的Datasheet PDF文件第6页浏览型号CY7C1061GE30-10BV1XIT的Datasheet PDF文件第7页 
CY7C1061G/CY7C1061GE  
16-Mbit (1M words × 16 bit) Static RAM  
with Error-Correcting Code (ECC)  
16-Mbit (1M words  
× 16 bit) Static RAM with Error-Correcting Code (ECC)  
To access devices with a single chip enable input, assert the chip  
enable (CE) input LOW. To access dual chip enable devices,  
assert both chip enable inputs – CE1 as LOW and CE2 as HIGH.  
Features  
■ High speed  
❐ tAA = 10 ns/15 ns  
To perform data writes, assert the Write Enable (WE) input LOW,  
and provide the data and address on the device data pins (I/O0  
through I/O15) and address pins (A0 through A19) respectively.  
The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs  
control byte writes, and write data on the corresponding I/O lines  
to the memory location specified. BHE controls I/O8 through  
I/O15 and BLE controls I/O0 through I/O7.  
■ Embedded error-correcting code (ECC) for single-bit error  
correction  
■ Low active and standby currents  
❐ ICC = 90 mA typical at 100 MHz  
❐ ISB2 = 20 mA typical  
■ Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and  
4.5 V to 5.5 V  
To perform data reads, assert the Output Enable (OE) input and  
provide the required address on the address lines. Read data is  
accessible on I/O lines (I/O0 through I/O15). You can perform  
byte accesses by asserting the required byte enable signal (BHE  
or BLE) to read either the upper byte or the lower byte of data  
from the specified address location.  
■ 1.0 V data retention  
■ Transistor-transistor logic (TTL) compatible inputs and outputs  
■ Error indication (ERR) pin to indicate 1-bit error detection and  
correction  
All I/Os (I/O0 through I/O15) are placed in a high-impedance state  
when the device is deselected (CE HIGH for a single chip enable  
device and CE1 HIGH / CE2 LOW for a dual chip enable device),  
or control signals are de-asserted (OE, BLE, BHE).  
■ Available in Pb-free 48-pin TSOP I, 54-pin TSOP II, and 48-ball  
VFBGA packages  
Functional Description  
On the CY7C1061GE devices, the detection and correction of a  
single-bit error in the accessed location is indicated by the  
assertion of the ERR output (ERR = High). See the Truth Table  
on page 16 for a complete description of read and write modes.  
CY7C1061G and CY7C1061GE are high-performance CMOS  
fast static RAM devices with embedded ECC[1]. Both devices are  
offered in single and dual chip enable options and in multiple pin  
configurations. The CY7C1061GE device includes an ERR pin  
that signals a single-bit error-detection and correction event  
during a read cycle.  
The logic block diagrams are on page 2.  
The CY7C1061G and CY7C1061GE devices are available in  
48-pin TSOP I, 54-pin TSOP II, and 48-ball VFBGA packages.  
For a complete list of related documentation, click here.  
Product Portfolio  
Current Consumption  
Features and Options  
Speed  
(ns)  
Operating ICC, (mA)  
f = fmax  
VCC Range  
(V)  
Product  
(see PinConfigurationson  
page 4)  
Range  
Standby, ISB2 (mA)  
10/15  
Typ[2]  
Max  
80  
Typ[2]  
Max  
CY7C1061G18 Single or dual chip enables  
Industrial 1.65 V–2.2 V  
2.2 V–3.6 V  
15  
10  
10  
70  
20  
30  
CY7C1061G(E)30  
Optional ERR pins  
90  
110  
110  
CY7C1061G  
4.5 V–5.5 V  
90  
Address MSB A19 pin  
placement options  
compatiblewithCypressand  
other vendors  
Notes  
1. This device does not support automatic write-back on error detection.  
2. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for a V range of 1.65 V–2.2 V),  
CC  
CC  
V
= 3 V (for a V range of 2.2 V–3.6 V), and V = 5 V (for a V range of 4.5 V–5.5 V), T = 25 °C.  
CC  
CC CC CC A  
Cypress Semiconductor Corporation  
Document Number: 001-81540 Rev. *S  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised June 16, 2017  
 
 
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CY7C1061GE30-10BVJXI INFINEON

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CY7C1061GE30-10BVJXIT INFINEON

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CY7C1061GE30-10BVXI CYPRESS

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 		Standard SRAM, 1MX16, 10ns, CMOS, PBGA48, VFBGA-48
CY7C1061GE30-10BVXI INFINEON

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CY7C1061GE30-10BVXIT INFINEON

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CY7C1061GE30-10ZSXI CYPRESS

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 		Standard SRAM, 1MX16, 10ns, CMOS, PDSO54, TSOP2-54
CY7C1061GE30-10ZSXI INFINEON

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 		Asynchronous SRAM
CY7C1061GE30-10ZSXIT CYPRESS

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 		Standard SRAM, 1MX16, 10ns, CMOS, PDSO54, TSOP2-54
CY7C1061GE30-10ZSXIT INFINEON

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 		Asynchronous SRAM
CY7C1061GE30-10ZXI CYPRESS

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 		Standard SRAM, 1MX16, 10ns, CMOS, PDSO48, TSOP1-48

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