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CY7C1049D

更新时间： 2024-09-17 05:19:03
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赛普拉斯 - CYPRESS /
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8页 391K
描述
4-Mbit (512K x 8) Static RAM

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CY7C1049D 数据手册

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CY7C1049D  
4-Mbit (512K x 8) Static RAM  
Features  
Functional Description[1]  
• Pin- and function-compatible with CY7C1049B  
• High speed  
The CY7C1049D is a high-performance CMOS static RAM  
organized as 512K words by 8 bits. Easy memory expansion  
is provided by an active LOW Chip Enable (CE), an active  
LOW Output Enable (OE), and tri-state drivers. Writing to the  
device is accomplished by taking Chip Enable (CE) and Write  
Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0  
through I/O7) is then written into the location specified on the  
address pins (A0 through A18).  
— tAA = 10 ns  
• Low active power  
— ICC = 90 mA @ 10 ns  
• Low CMOS Standby power  
— ISB2 = 10 mA  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing Write  
Enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins will appear  
on the I/O pins.  
• 2.0V Data Retention  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE and OE features  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW, and WE LOW).  
• Available in lead-free 36-Lead (400-Mil) Molded SOJ  
package  
The CY7C1049D is available in a standard 400-mil-wide  
36-pin SOJ package with center power and ground (revolu-  
tionary) pinout.  
Logic Block Diagram  
Pin Configuration  
SOJ  
Top View  
A
A
36  
35  
34  
33  
1
NC  
0
1
2
3
4
A
A
A
A
18  
17  
16  
15  
A
2
A
A
3
4
32  
31  
30  
29  
28  
27  
26  
25  
5
I/O  
CE  
I/O  
0
6
OE  
I/O  
INPUT BUFFER  
7
8
9
10  
11  
12  
13  
0
1
7
I/O  
I/O  
V
A
0
6
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
1
A
GND  
CC  
1
GND  
I/O  
I/O3  
WE  
A
V
2
CC  
2
I/O  
I/O  
A
A
A
A
2
5
4
3
A
4
24  
23  
22  
21  
20  
19  
A
14  
13  
12  
5
3
4
5
512K x 8  
A
5
A
A
7
A
A
14  
15  
16  
17  
18  
6
A
6
7
A
A
A
11  
10  
8
9
A
8
A
9
NC  
A
10  
6
7
POWER  
DOWN  
COLUMN  
DECODER  
CE  
I/O  
WE  
OE  
Selection Guide  
-10  
10  
90  
10  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
mA  
mA  
Maximum CMOS Standby Current  
Note:  
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05474 Rev. *C  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised April 3, 2006  
[+] Feedback  
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CY7C1049DV33-10VXI CYPRESS

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 		4-Mbit (512K x 8) Static RAM
CY7C1049DV33-10VXI ROCHESTER

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