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CY7C1049CV33-8ZSXCT PDF预览

CY7C1049CV33-8ZSXCT

更新时间: 2024-09-17 21:06:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
14页 323K
描述
Application Specific SRAM, 512KX8, 10ns, CMOS, PDSO44, LEAD FREE, TSOP2-44

CY7C1049CV33-8ZSXCT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete包装说明:TSOP2, TSOP44,.46,32
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:10 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-G44JESD-609代码:e4
长度:18.415 mm内存密度:4194304 bit
内存集成电路类型:APPLICATION SPECIFIC SRAM内存宽度:8
湿度敏感等级:3功能数量:1
端子数量:44字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:512KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装等效代码:TSOP44,.46,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:1.194 mm
最大待机电流:0.01 A最小待机电流:3 V
子类别:SRAMs最大压摆率:0.1 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:10.16 mm
Base Number Matches:1

CY7C1049CV33-8ZSXCT 数据手册

 浏览型号CY7C1049CV33-8ZSXCT的Datasheet PDF文件第2页浏览型号CY7C1049CV33-8ZSXCT的Datasheet PDF文件第3页浏览型号CY7C1049CV33-8ZSXCT的Datasheet PDF文件第4页浏览型号CY7C1049CV33-8ZSXCT的Datasheet PDF文件第5页浏览型号CY7C1049CV33-8ZSXCT的Datasheet PDF文件第6页浏览型号CY7C1049CV33-8ZSXCT的Datasheet PDF文件第7页 
CY7C1049CV33  
4-Mbit (512 K × 8) Static RAM  
4-Mbit (512  
K × 8) Static RAM  
Features  
Functional Description  
Temperature ranges  
Commercial: 0 °C to 70 °C  
The CY7C1049CV33 is a high performance Complementary  
metal oxide semiconductor (CMOS) Static RAM organized as  
524,288 words by eight bits. Easy memory expansion is provided  
by an active LOW Chip Enable (CE), an active LOW Output  
Enable (OE), and three-state drivers. Writing to the device is  
accomplished by taking Chip Enable (CE) and Write Enable  
(WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7)  
is then written into the location specified on the address pins (A0  
through A18).  
High speed  
tAA = 8 ns  
Low active power  
360 mW (max)  
2.0 V data retention  
Reading from the device is accomplished by taking Chip Enable  
(CE) and Output Enable (OE) LOW while forcing Write Enable  
(WE) HIGH. Under these conditions, the contents of the memory  
location specified by the address pins appear on the I/O pins.  
Automatic power down when deselected  
Transistor- transistor logic (TTL) compatible inputs and outputs  
Easy memory expansion with CE and OE features  
The eight input and output pins (I/O0 through I/O7) are placed in  
a high impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW, and WE LOW).  
The CY7C1049CV33 is available in standard 44-pin TSOP II  
package with center power and ground (revolutionary) pinout.  
Logic Block Diagram  
A
0
IO  
0
INPUT BUFFER  
A
1
A
2
IO  
1
A
3
A
4
IO  
2
A
5
A
6
512K x 8  
ARRAY  
IO  
3
A
A
A
A
A
A
7
8
IO  
4
9
10  
11  
12  
IO  
5
IO  
6
CE  
IO  
POWER  
DOWN  
7
COLUMN DECODER  
WE  
OE  
Cypress Semiconductor Corporation  
Document Number: 38-05006 Rev. *N  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised November 16, 2011  
[+] Feedback  

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