Datasheet > CY7C1021CV33-15BAXIT

CY7C1021CV33-15BAXIT

更新时间： 2024-11-12 10:05:03

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
14页	554K
描述
Standard SRAM, 64KX16, 15ns, CMOS, PBGA48, 7 X 7 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-48

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CY7C1021CV33

1-Mbit (64K x 16) Static RAM

Features

Functional Description

■ Temperature ranges

The CY7C1021CV33 is a high performance CMOS static RAM

organized as 65,536 words by 16 bits. This device has an

automatic power down feature that significantly reduces power

consumption when deselected.

❐ Commercial: 0°C to 70°C

❐ Industrial: –40°C to 85°C

❐ Automotive-A: –40°C to 85°C

❐ Automotive-E: –40°C to 125°C

Writing to the device is accomplished by taking Chip Enable (CE)

and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is

LOW, then data from IO pins (IO₁through IO₈), is written into the

location specified on the address pins (A₀through A₁₅). If Byte

High Enable (BHE) is LOW, then data from IO pins (IO₉through

IO₁₆) is written into the location specified on the address pins (A₀

through A₁₅).

■ Pin and function compatible with CY7C1021BV33

■ High speed

❐ t_AA= 8 ns (Commercial & Industrial)

❐ t_AA= 12 ns (Automotive-E)

■ CMOS for optimum speed and power

■ Low active power: 325 mW (max)

Reading from the device is accomplished by taking Chip Enable

(CE) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data

from the memory location specified by the address pins appear

on IO₁to IO₈. If Byte High Enable (BHE) is LOW, then data from

memory appears on IO₉to IO₁₆. For more information, see the

“Truth Table” on page 9 for a complete description of Read and

Write modes.

■ Automatic power down when deselected

■ Independent control of upper and lower bits

■ AvailableinPb-freeandnonPb-free44-pin400MilSOJ, 44-pin

TSOP II and 48-Ball FBGA packages

The input and output pins (IO₁through IO₁₆) are placed in a high

impedance state when the device is deselected (CE HIGH), the

outputs are disabled (OE HIGH), the BHE and BLE are disabled

(BHE, BLE HIGH), or during a write operation (CE LOW and WE

LOW).

For best practice recommendations, refer to the Cypress

application note AN1064, SRAM System Guidelines.

Logic Block Diagram

DATA IN DRIVERS

A₇

A₆

A₅

64K x 16

A₄

IO₀–IO₇

RAM Array

A₃

A₂

A₁

A₀

IO₈–IO₁₅

COLUMN DECODER

BHE

BLE

Cypress Semiconductor Corporation

Document Number: 38-05132 Rev. *H

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised October 11, 2007

12 3 4 5 6 7...14

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与CY7C1021CV33-15BAXIT相关器件

型号	品牌	获取价格	描述	数据表
CY7C1021CV33-15VC	CYPRESS	获取价格	64K x 16 Static RAM
CY7C1021CV33-15VC	ROCHESTER	获取价格	Standard SRAM, 64KX16, 15ns, CMOS, PDSO44, 0.400 INCH, SOJ-44
CY7C1021CV33-15VCT	CYPRESS	获取价格	Standard SRAM, 64KX16, 15ns, CMOS, PDSO44, 0.400 INCH, SOJ-44
CY7C1021CV33-15VI	CYPRESS	获取价格	64K x 16 Static RAM
CY7C1021CV33-15VIT	CYPRESS	获取价格	Standard SRAM, 64KX16, 15ns, CMOS, PDSO44, 0.400 INCH, SOJ-44
CY7C1021CV33-15VIT	ROCHESTER	获取价格	Standard SRAM, 64KX16, 15ns, CMOS, PDSO44, 0.400 INCH, SOJ-44
CY7C1021CV33-15VXC	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY7C1021CV33-15VXC	ROCHESTER	获取价格	Standard SRAM, 64KX16, 15ns, CMOS, PDSO44, 0.400 INCH, LEAD FREE, SOJ-44
CY7C1021CV33-15VXCT	ROCHESTER	获取价格	Standard SRAM, 64KX16, 15ns, CMOS, PDSO44, 0.400 INCH, LEAD FREE, SOJ-44
CY7C1021CV33-15VXI	CYPRESS	获取价格	Standard SRAM, 64KX16, 15ns, CMOS, PDSO44, 0.400 INCH, LEAD FREE, SOJ-44

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