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CY7C1021BNL-15ZSXAT PDF预览

CY7C1021BNL-15ZSXAT

更新时间： 2024-11-23 13:07:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
14页 503K
描述
Standard SRAM, 64KX16, 15ns, CMOS, PDSO44,

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CY7C1021BNL-15ZSXAT 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：TSOP, TSOP44,.46,32Reach Compliance Code：compliant
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
Factory Lead Time：1 week风险等级：5.8
最长访问时间：15 nsI/O 类型：COMMON
JESD-30 代码：R-PDSO-G44内存密度：1048576 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
端子数量：44字数：65536 words
字数代码：64000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：64KX16输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSOP
封装等效代码：TSOP44,.46,32封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE并行/串行：PARALLEL
电源：5 V认证状态：Not Qualified
筛选级别：AEC-Q100最大待机电流：0.0005 A
最小待机电流：4.5 V子类别：SRAMs
最大压摆率：0.13 mA标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.8 mm端子位置：DUAL
Base Number Matches：1

CY7C1021BNL-15ZSXAT 数据手册

 浏览型号CY7C1021BNL-15ZSXAT的Datasheet PDF文件第2页浏览型号CY7C1021BNL-15ZSXAT的Datasheet PDF文件第3页浏览型号CY7C1021BNL-15ZSXAT的Datasheet PDF文件第4页浏览型号CY7C1021BNL-15ZSXAT的Datasheet PDF文件第5页浏览型号CY7C1021BNL-15ZSXAT的Datasheet PDF文件第6页浏览型号CY7C1021BNL-15ZSXAT的Datasheet PDF文件第7页 
CY7C1021BN, CY7C10211BN  
1-Mbit (64 K × 16) Static RAM  
1-Mbit (64  
K × 16) Static RAM  
Features  
Functional Description  
■ Temperature ranges  
The CY7C1021BN/CY7C10211BN is a high performance CMOS  
static RAM organized as 65,536 words by 16 bits. This device  
has an automatic power down feature that significantly reduces  
power consumption when deselected.  
❐ Commercial: 0 °C to 70 °C  
❐ Industrial: –40 °C to 85 °C  
❐ Automotive-A: –40 °C to 85 °C  
❐ Automotive-E: –40 °C to 125 °C  
Writing to the device is accomplished by taking Chip Enable (CE)  
and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is  
LOW, then data from the input/output (I/O) pins (I/O1 through  
I/O8), is written into the location specified on the address pins (A0  
through A15). If Byte High Enable (BHE) is LOW, then data from  
I/O pins (I/O9 through I/O16) is written into the location specified  
on the address pins (A0 through A15).  
■ High speed  
❐ tAA = 15 ns (Automotive)  
■ Complementary metal oxide semiconductor (CMOS) for  
optimum speed/power  
■ Low active power  
❐ 825 mW (maximum)  
Reading from the device is accomplished by taking CE and  
Output Enable (OE) LOW while forcing WE HIGH. If BLE is LOW,  
then data from the memory location specified by the address pins  
appears on I/O1 to I/O8. If BHE is LOW, then data from memory  
appears on I/O9 to I/O16. See the Truth Table on page 9 for a  
complete description of read and write modes.  
■ Automatic power down when deselected  
■ Independent control of upper and lower bits  
■ Available in Pb-free and non Pb-free 44-pin TSOP II and 44-pin  
400-mil-wide SOJ  
The I/O pins (I/O1 through I/O16) are placed in a high impedance  
state when the device is deselected (CE HIGH), the outputs are  
disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE  
HIGH), or during a write operation (CE LOW, WE LOW).  
The CY7C1021BN/CY7C10211BN is available in standard  
44-pin TSOP type II and 44-pin 400-mil-wide SOJ packages.  
Use part number CY7C1021BN when ordering 15 ns tAA  
.
Logic Block Diagram  
Data In Drivers  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
64K x 16  
I/O1–I/O8  
RAM Array  
512 X 2048  
I/O9–I/O16  
A0  
Column Decoder  
BHE  
WE  
CE  
OE  
BLE  
Cypress Semiconductor Corporation  
Document #: 001-06494 Rev. *D  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised July 26, 2011  
[+] Feedback  
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